sb/intel/i82801[ij]x: use (more) RCBA register names instead of magic numbers
Change-Id: I909d7dd4968aa2f76df00c03e603e8e82a4824c0
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c
index e47586b..24fe347 100644
--- a/src/southbridge/intel/i82801ix/dmi_setup.c
+++ b/src/southbridge/intel/i82801ix/dmi_setup.c
@@ -46,11 +46,12 @@
RCBA32(RCBA_V1CAP) = (RCBA32(RCBA_V1CAP) & ~(0x7f<<16)) | (0x12<<16);
- RCBA32(0x0088) = 0x00109000;
- RCBA16(0x01fc) = 0x060b;
- RCBA32(0x01f4) = 0x86000040;
- RCBA8 (0x0220) = 0x45;
- RCBA32(0x2024) &= ~(1 << 7);
+ /* NB: other CIRs are handled in i82801ix_early_settings(). */
+ RCBA32(RCBA_CIR1) = 0x00109000;
+ RCBA16(RCBA_CIR3) = 0x060b;
+ RCBA32(RCBA_CIR2) = 0x86000040;
+ RCBA8(RCBA_BCR) = 0x45;
+ RCBA32(RCBA_CIR6) &= ~(1 << 7);
/* VC1 setup for isochronous transfers: */
diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c
index 7247132..7e91ba1 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.c
+++ b/src/southbridge/intel/i82801ix/i82801ix.c
@@ -38,15 +38,16 @@
static void i82801ix_early_settings(const config_t *const info)
{
/* Program FERR# as processor break event indicator. */
- RCBA32(0x3410) |= (1 << 6);
- /* BIOS must program... */
- RCBA32(0x3430) = (RCBA32(0x3430) & ~(0x3 << 0)) | (0x2 << 0);
- RCBA32(0x3418) |= (1 << 0);
- RCBA32(0x350c) = (RCBA32(0x350c) & ~(0x3 << 26)) | (0x2 << 26);
- RCBA32(0x2034) = (RCBA32(0x2034) & ~(0xf << 16)) | (0x5 << 16);
- RCBA32(0x0f20) = (RCBA32(0x0f20) & ~(0xf << 16)) | (0x5 << 16);
- RCBA32(0x1d40) |= (1 << 0);
- RCBA32(0x352c) |= (3 << 16);
+ RCBA32(GCS) |= (1 << 6);
+ /* BIOS must program...
+ * NB: other CIRs are handled in i82801ix_dmi_setup(). */
+ RCBA32(RCBA_CIR8) = (RCBA32(RCBA_CIR8) & ~(0x3 << 0)) | (0x2 << 0);
+ RCBA32(RCBA_FD) |= (1 << 0);
+ RCBA32(RCBA_CIR9) = (RCBA32(RCBA_CIR9) & ~(0x3 << 26)) | (0x2 << 26);
+ RCBA32(RCBA_CIR7) = (RCBA32(RCBA_CIR7) & ~(0xf << 16)) | (0x5 << 16);
+ RCBA32(RCBA_CIR13) = (RCBA32(RCBA_CIR13) & ~(0xf << 16)) | (0x5 << 16);
+ RCBA32(RCBA_CIR5) |= (1 << 0);
+ RCBA32(RCBA_CIR10) |= (3 << 16);
}
static void i82801ix_pcie_init(const config_t *const info)
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
index b70c7f8..aed1999 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.h
+++ b/src/southbridge/intel/i82801ix/i82801ix.h
@@ -156,20 +156,32 @@
#define RCBA_V1CTL 0x0020
#define RCBA_V1STS 0x0026
#define RCBA_PAT 0x0030
+#define RCBA_CIR1 0x0088
#define RCBA_ESD 0x0104
#define RCBA_ULD 0x0110
#define RCBA_ULBA 0x0118
#define RCBA_LCAP 0x01a4
#define RCBA_LCTL 0x01a8
#define RCBA_LSTS 0x01aa
+#define RCBA_CIR2 0x01f4
+#define RCBA_CIR3 0x01fc
+#define RCBA_BCR 0x0220
#define RCBA_DMIC 0x0234
#define RCBA_RPFN 0x0238
+#define RCBA_CIR13 0x0f20
+#define RCBA_CIR5 0x1d40
#define RCBA_DMC 0x2010
+#define RCBA_CIR6 0x2024
+#define RCBA_CIR7 0x2034
#define RCBA_HPTC 0x3404
+#define GCS 0x3410
#define RCBA_BUC 0x3414
#define RCBA_FD 0x3418 /* Function Disable, see below. */
#define RCBA_CG 0x341c
#define RCBA_FDSW 0x3420
+#define RCBA_CIR8 0x3430
+#define RCBA_CIR9 0x350c
+#define RCBA_CIR10 0x352c
#define RCBA_MAP 0x35f0 /* UHCI controller #6 remapping */
#define BUC_LAND (1 << 5) /* LAN */
diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c
index 548a595..2afe3b5 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.c
+++ b/src/southbridge/intel/i82801jx/i82801jx.c
@@ -38,15 +38,15 @@
static void i82801jx_early_settings(const config_t *const info)
{
/* Program FERR# as processor break event indicator. */
- RCBA32(0x3410) |= (1 << 6);
+ RCBA32(GCS) |= (1 << 6);
/* BIOS must program... */
- RCBA32(0x3430) = (RCBA32(0x3430) & ~(0x3 << 0)) | (0x2 << 0);
- RCBA32(0x3418) |= (1 << 0);
- RCBA32(0x350c) = (RCBA32(0x350c) & ~(0x3 << 26)) | (0x2 << 26);
- RCBA32(0x2034) = (RCBA32(0x2034) & ~(0xf << 16)) | (0x5 << 16);
- RCBA32(0x0f20) = (RCBA32(0x0f20) & ~(0xf << 16)) | (0x5 << 16);
- RCBA32(0x1d40) |= (1 << 0);
- RCBA32(0x352c) |= (3 << 16);
+ RCBA32(RCBA_CIR8) = (RCBA32(RCBA_CIR8) & ~(0x3 << 0)) | (0x2 << 0);
+ RCBA32(RCBA_FD) |= (1 << 0);
+ RCBA32(RCBA_CIR9) = (RCBA32(RCBA_CIR9) & ~(0x3 << 26)) | (0x2 << 26);
+ RCBA32(RCBA_CIR7) = (RCBA32(RCBA_CIR7) & ~(0xf << 16)) | (0x5 << 16);
+ RCBA32(RCBA_CIR13) = (RCBA32(RCBA_CIR13) & ~(0xf << 16)) | (0x5 << 16);
+ RCBA32(RCBA_CIR5) |= (1 << 0);
+ RCBA32(RCBA_CIR10) |= (3 << 16);
}
static void i82801jx_pcie_init(const config_t *const info)
diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h
index 5aa41dd..2e2d719 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.h
+++ b/src/southbridge/intel/i82801jx/i82801jx.h
@@ -149,21 +149,32 @@
#define RCBA_V1CTL 0x0020
#define RCBA_V1STS 0x0026
#define RCBA_PAT 0x0030
+#define RCBA_CIR1 0x0088
#define RCBA_ESD 0x0104
#define RCBA_ULD 0x0110
#define RCBA_ULBA 0x0118
#define RCBA_LCAP 0x01a4
#define RCBA_LCTL 0x01a8
#define RCBA_LSTS 0x01aa
+#define RCBA_CIR2 0x01f4
+#define RCBA_CIR3 0x01fc
+#define RCBA_BCR 0x0220
#define RCBA_DMIC 0x0234
#define RCBA_RPFN 0x0238
+#define RCBA_CIR13 0x0f20
+#define RCBA_CIR5 0x1d40
#define RCBA_DMC 0x2010
+#define RCBA_CIR6 0x2024
+#define RCBA_CIR7 0x2034
#define RCBA_HPTC 0x3404
#define GCS 0x3410
#define RCBA_BUC 0x3414
#define RCBA_FD 0x3418 /* Function Disable, see below. */
#define RCBA_CG 0x341c
#define RCBA_FDSW 0x3420
+#define RCBA_CIR8 0x3430
+#define RCBA_CIR9 0x350c
+#define RCBA_CIR10 0x352c
#define RCBA_MAP 0x35f0 /* UHCI controller #6 remapping */
#define D31IP 0x3100 /* 32bit */