oops. this is weird. CAR addresses should be specified in the socket and not in
the board. I thought we did this ages ago.
Also push CAR BASE further down so it won't conflict with a 32mbit flash part.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig
index 1306656..f73c8a9 100644
--- a/src/cpu/intel/socket_441/Kconfig
+++ b/src/cpu/intel/socket_441/Kconfig
@@ -12,7 +12,7 @@
config DCACHE_RAM_BASE
hex
- default 0xffdf8000
+ default 0xffaf8000
config DCACHE_RAM_SIZE
hex
diff --git a/src/cpu/intel/socket_mFCPGA478/Kconfig b/src/cpu/intel/socket_mFCPGA478/Kconfig
index b8a3508..3f39303 100644
--- a/src/cpu/intel/socket_mFCPGA478/Kconfig
+++ b/src/cpu/intel/socket_mFCPGA478/Kconfig
@@ -1,3 +1,22 @@
config CPU_INTEL_SOCKET_MFCPGA478
bool
+
+if CPU_INTEL_SOCKET_MFCPGA478
+
+config SOCKET_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_INTEL_CORE
+ select CPU_INTEL_CORE2
+ select MMX
+ select SSE
select CACHE_AS_RAM
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xffaf8000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+
+endif
diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig
index ed05a30..f531a51 100644
--- a/src/mainboard/getac/p470/Kconfig
+++ b/src/mainboard/getac/p470/Kconfig
@@ -21,7 +21,6 @@
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select CPU_INTEL_CORE
select CPU_INTEL_SOCKET_MFCPGA478
select NORTHBRIDGE_INTEL_I945GM
select SOUTHBRIDGE_INTEL_I82801GX
@@ -48,14 +47,6 @@
string
default getac/p470
-config DCACHE_RAM_BASE
- hex
- default 0xffdf8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x8000
-
config MAINBOARD_PART_NUMBER
string
default "P470"
diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig
index 0d4adb7..3569e35 100644
--- a/src/mainboard/ibase/mb899/Kconfig
+++ b/src/mainboard/ibase/mb899/Kconfig
@@ -3,7 +3,6 @@
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select CPU_INTEL_CORE
select CPU_INTEL_SOCKET_MFCPGA478
select NORTHBRIDGE_INTEL_I945GM
select SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig b/src/mainboard/iwave/iWRainbowG6/Kconfig
index fdd7db6..7005bd3 100644
--- a/src/mainboard/iwave/iWRainbowG6/Kconfig
+++ b/src/mainboard/iwave/iWRainbowG6/Kconfig
@@ -4,7 +4,6 @@
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select CPU_INTEL_CORE # FIXME
select CPU_INTEL_SOCKET_441
select NORTHBRIDGE_INTEL_SCH
select SOUTHBRIDGE_INTEL_SCH
diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig
index e1d3a11..e242afd 100644
--- a/src/mainboard/kontron/986lcd-m/Kconfig
+++ b/src/mainboard/kontron/986lcd-m/Kconfig
@@ -3,7 +3,6 @@
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select CPU_INTEL_CORE
select CPU_INTEL_SOCKET_MFCPGA478
select NORTHBRIDGE_INTEL_I945GM
select SOUTHBRIDGE_INTEL_I82801GX
@@ -26,14 +25,6 @@
string
default kontron/986lcd-m
-config DCACHE_RAM_BASE
- hex
- default 0xffdf8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x8000
-
config MAINBOARD_PART_NUMBER
string
default "986LCD-M"
diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig
index b3a3e8f..d80a4cc 100644
--- a/src/mainboard/roda/rk886ex/Kconfig
+++ b/src/mainboard/roda/rk886ex/Kconfig
@@ -25,14 +25,6 @@
string
default roda/rk886ex
-config DCACHE_RAM_BASE
- hex
- default 0xffdf8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x8000
-
config MAINBOARD_PART_NUMBER
string
default "RK886EX"