commit cdf7ec6faa60f8f6a5650214a6bc9bb30f32e13e
author Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Wed Dec 28 14:15:53 2022 +0600
committer Martin L Roth <gaumless@gmail.com> Wed Jan 04 07:02:24 2023 +0000
tree 97614b495e2e80bc92820b0e86d370b943c3e822
parent 6f5be8ff3079f31c0c46508c8b1c4473aed05658

mb/google/nissa/var/yaviks: Disable external fivr

In next phase, yaviks will remove external fivr. Use the board version
to config external fivr for backward compatibility and show message.

BUG=b:263842258
TEST=build, boot to OS, suspend/resume work normally.

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Id85570046c5b8e9d90a112793c1ec8604e6bf533
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>

src/mainboard/google/brya/variants/yaviks/overridetree.cb

diff --git a/src/mainboard/google/brya/variants/yaviks/overridetree.cb b/src/mainboard/google/brya/variants/yaviks/overridetree.cb
index d84fccd..7343aa7 100644
--- a/src/mainboard/google/brya/variants/yaviks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/yaviks/overridetree.cb
@@ -24,16 +24,6 @@
 	# Configure external V1P05/Vnn/VnnSx Rails
 	register "ext_fivr_settings" = "{
 		.configure_ext_fivr = 1,
-		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
-		.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
-		.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
-		.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
-		.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
-		.v1p05_voltage_mv = 1050,
-		.vnn_voltage_mv = 780,
-		.vnn_sx_voltage_mv = 1050,
-		.v1p05_icc_max_ma = 500,
-		.vnn_icc_max_ma = 500,
 	}"
 
 	# Intel Common SoC Config

src/mainboard/google/brya/variants/yaviks/variant.c

diff --git a/src/mainboard/google/brya/variants/yaviks/variant.c b/src/mainboard/google/brya/variants/yaviks/variant.c
index 0db334d..f05f4f7 100644
--- a/src/mainboard/google/brya/variants/yaviks/variant.c
+++ b/src/mainboard/google/brya/variants/yaviks/variant.c
@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <baseboard/variants.h>
+#include <boardid.h>
 #include <fw_config.h>
 #include <sar.h>
 
@@ -10,3 +12,28 @@
 
 	return NULL;
 }
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+	const uint32_t id = board_id();
+	if (id == BOARD_ID_UNKNOWN || id < 4) { // proto, EVT
+		config->ext_fivr_settings.configure_ext_fivr = 1;
+
+		config->ext_fivr_settings.v1p05_enable_bitmap =
+				FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0;
+		config->ext_fivr_settings.vnn_enable_bitmap =
+				FIVR_ENABLE_ALL_SX;
+		config->ext_fivr_settings.vnn_sx_enable_bitmap =
+				FIVR_ENABLE_ALL_SX;
+		config->ext_fivr_settings.v1p05_supported_voltage_bitmap =
+				FIVR_VOLTAGE_NORMAL;
+		config->ext_fivr_settings.vnn_supported_voltage_bitmap =
+				FIVR_VOLTAGE_MIN_ACTIVE;
+		config->ext_fivr_settings.v1p05_voltage_mv = 1050;
+		config->ext_fivr_settings.vnn_voltage_mv = 780;
+		config->ext_fivr_settings.vnn_sx_voltage_mv = 1050;
+		config->ext_fivr_settings.v1p05_icc_max_ma = 500;
+		config->ext_fivr_settings.vnn_icc_max_ma = 500;
+		printk(BIOS_INFO, "Configured External FIVR\n");
+	}
+}