diff --git a/src/acpi/gnvs.c b/src/acpi/gnvs.c
index d1bbb01..827cd2d 100644
--- a/src/acpi/gnvs.c
+++ b/src/acpi/gnvs.c
@@ -31,8 +31,6 @@
 	if (dnvs_size)
 		dnvs = (char *)gnvs + gnvs_size;
 
-	if (CONFIG(CONSOLE_CBMEM))
-		gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
 }
 
 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, acpi_create_gnvs, NULL);
diff --git a/src/soc/amd/cezanne/acpi/globalnvs.asl b/src/soc/amd/cezanne/acpi/globalnvs.asl
index f4a6c5f..352bc71 100644
--- a/src/soc/amd/cezanne/acpi/globalnvs.asl
+++ b/src/soc/amd/cezanne/acpi/globalnvs.asl
@@ -8,7 +8,7 @@
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */
-	CBMC,	32,	// 0x00 - 0x03 - coreboot Memory Console
+	,	32,	// 0x00 - 0x03 - coreboot Memory Console
 	PM1I,	64,	// 0x04 - 0x0b - System Wake Source - PM1 Index
 	GPEI,	64,	// 0x0c - 0x13 - GPE Wake Source
 }
diff --git a/src/soc/amd/cezanne/include/soc/nvs.h b/src/soc/amd/cezanne/include/soc/nvs.h
index d1a8e30..1d98070 100644
--- a/src/soc/amd/cezanne/include/soc/nvs.h
+++ b/src/soc/amd/cezanne/include/soc/nvs.h
@@ -13,7 +13,7 @@
 
 struct __packed global_nvs {
 	/* Miscellaneous */
-	uint32_t	cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
+	uint32_t	unused_was_cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
 	uint64_t	pm1i; /* 0x04 - 0x0b - System Wake Source - PM1 Index */
 	uint64_t	gpei; /* 0x0c - 0x13 - GPE Wake Source */
 };
diff --git a/src/soc/amd/glinda/acpi/globalnvs.asl b/src/soc/amd/glinda/acpi/globalnvs.asl
index 512f9e8..0e3929d 100644
--- a/src/soc/amd/glinda/acpi/globalnvs.asl
+++ b/src/soc/amd/glinda/acpi/globalnvs.asl
@@ -8,7 +8,7 @@
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */
-	CBMC,	32,	// 0x00 - 0x03 - coreboot Memory Console
+	,	32,	// 0x00 - 0x03 - coreboot Memory Console
 	PM1I,	64,	// 0x04 - 0x0b - System Wake Source - PM1 Index
 	GPEI,	64,	// 0x0c - 0x13 - GPE Wake Source
 }
diff --git a/src/soc/amd/glinda/include/soc/nvs.h b/src/soc/amd/glinda/include/soc/nvs.h
index 1e663e4..2b1d17b 100644
--- a/src/soc/amd/glinda/include/soc/nvs.h
+++ b/src/soc/amd/glinda/include/soc/nvs.h
@@ -13,7 +13,7 @@
 
 struct __packed global_nvs {
 	/* Miscellaneous */
-	uint32_t	cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
+	uint32_t	unused_was_cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
 	uint64_t	pm1i; /* 0x04 - 0x0b - System Wake Source - PM1 Index */
 	uint64_t	gpei; /* 0x0c - 0x13 - GPE Wake Source */
 };
diff --git a/src/soc/amd/mendocino/acpi/globalnvs.asl b/src/soc/amd/mendocino/acpi/globalnvs.asl
index 4161e5f..7d1774d 100644
--- a/src/soc/amd/mendocino/acpi/globalnvs.asl
+++ b/src/soc/amd/mendocino/acpi/globalnvs.asl
@@ -8,7 +8,7 @@
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */
-	CBMC,	32,	// 0x00 - 0x03 - coreboot Memory Console
+	,	32,	// 0x00 - 0x03 - coreboot Memory Console
 	PM1I,	64,	// 0x04 - 0x0b - System Wake Source - PM1 Index
 	GPEI,	64,	// 0x0c - 0x13 - GPE Wake Source
 }
diff --git a/src/soc/amd/mendocino/include/soc/nvs.h b/src/soc/amd/mendocino/include/soc/nvs.h
index 928a310..3d50e08 100644
--- a/src/soc/amd/mendocino/include/soc/nvs.h
+++ b/src/soc/amd/mendocino/include/soc/nvs.h
@@ -13,7 +13,7 @@
 
 struct __packed global_nvs {
 	/* Miscellaneous */
-	uint32_t	cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
+	uint32_t	unused_was_cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
 	uint64_t	pm1i; /* 0x04 - 0x0b - System Wake Source - PM1 Index */
 	uint64_t	gpei; /* 0x0c - 0x13 - GPE Wake Source */
 };
diff --git a/src/soc/amd/phoenix/acpi/globalnvs.asl b/src/soc/amd/phoenix/acpi/globalnvs.asl
index f5a6aa5..13f01e5 100644
--- a/src/soc/amd/phoenix/acpi/globalnvs.asl
+++ b/src/soc/amd/phoenix/acpi/globalnvs.asl
@@ -8,7 +8,7 @@
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */
-	CBMC,	32,	// 0x00 - 0x03 - coreboot Memory Console
+	,	32,	// 0x00 - 0x03 - coreboot Memory Console
 	PM1I,	64,	// 0x04 - 0x0b - System Wake Source - PM1 Index
 	GPEI,	64,	// 0x0c - 0x13 - GPE Wake Source
 }
diff --git a/src/soc/amd/phoenix/include/soc/nvs.h b/src/soc/amd/phoenix/include/soc/nvs.h
index 35f27aa..6e0de9e 100644
--- a/src/soc/amd/phoenix/include/soc/nvs.h
+++ b/src/soc/amd/phoenix/include/soc/nvs.h
@@ -13,7 +13,7 @@
 
 struct __packed global_nvs {
 	/* Miscellaneous */
-	uint32_t	cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
+	uint32_t	unused_was_cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
 	uint64_t	pm1i; /* 0x04 - 0x0b - System Wake Source - PM1 Index */
 	uint64_t	gpei; /* 0x0c - 0x13 - GPE Wake Source */
 };
diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl
index 2d24b88..c322a4c 100644
--- a/src/soc/amd/picasso/acpi/globalnvs.asl
+++ b/src/soc/amd/picasso/acpi/globalnvs.asl
@@ -9,7 +9,7 @@
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */
-	CBMC,	32,	// 0x00 - 0x03 - coreboot Memory Console
+	,	32,	// 0x00 - 0x03 - coreboot Memory Console
 	PM1I,	64,	// 0x04 - 0x0b - System Wake Source - PM1 Index
 	GPEI,	64,	// 0x0c - 0x13 - GPE Wake Source
 	TMPS,	8,	// 0x14 - Temperature Sensor ID
diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h
index c5821bb..12cff4b 100644
--- a/src/soc/amd/picasso/include/soc/nvs.h
+++ b/src/soc/amd/picasso/include/soc/nvs.h
@@ -14,7 +14,7 @@
 
 struct __packed global_nvs {
 	/* Miscellaneous */
-	uint32_t	cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
+	uint32_t	unused_was_cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
 	uint64_t	pm1i; /* 0x04 - 0x0b - System Wake Source - PM1 Index */
 	uint64_t	gpei; /* 0x0c - 0x13 - GPE Wake Source */
 	uint8_t		tmps; /* 0x14 - Temperature Sensor ID */
diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl
index 7f3fe1b..0c1c4d1 100644
--- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl
+++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl
@@ -9,7 +9,7 @@
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */
-	CBMC,	32,	// 0x00 - 0x03 - coreboot Memory Console
+	,	32,	// 0x00 - 0x03 - coreboot Memory Console
 	PM1I,	64,	// 0x04 - 0x0b - System Wake Source - PM1 Index
 	GPEI,	64,	// 0x0c - 0x13 - GPE Wake Source
 	TMPS,	8,	// 0x14 - Temperature Sensor ID
diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h
index eaaf1bd..226c9f6 100644
--- a/src/soc/amd/stoneyridge/include/soc/nvs.h
+++ b/src/soc/amd/stoneyridge/include/soc/nvs.h
@@ -14,7 +14,7 @@
 
 struct __packed global_nvs {
 	/* Miscellaneous */
-	uint32_t	cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
+	uint32_t	unused_was_cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
 	uint64_t	pm1i; /* 0x04 - 0x0b - System Wake Source - PM1 Index */
 	uint64_t	gpei; /* 0x0c - 0x13 - GPE Wake Source */
 	uint8_t		tmps; /* 0x14 - Temperature Sensor ID */
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index a56d2e1..ad5119c 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -14,7 +14,7 @@
 	LIDS,	8,      // 0x02 - LID State
 	,	8,      // 0x03 - AC Power State
 	DPTE,	8,      // 0x04 - Enable DPTF
-	CBMC,	32,     // 0x05 - 0x08 - coreboot Memory Console
+	,	32,     // 0x05 - 0x08 - coreboot Memory Console
 	PM1I,	64,     // 0x09 - 0x10 - System Wake Source - PM1 Index
 	GPEI,	64,     // 0x11 - 0x18 - GPE Wake Source
 	NHLA,	64,     // 0x19 - 0x20 - NHLT Address
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index 95d9ab4..c1f575b 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -18,7 +18,7 @@
 	uint8_t		lids; /* 0x02 - LID State */
 	uint8_t		unused_was_pwrs; /* 0x03 - AC Power State */
 	uint8_t		dpte; /* 0x04 - Enable DPTF */
-	uint32_t	cbmc; /* 0x05 - 0x08 - coreboot Memory Console */
+	uint32_t	unused_was_cbmc; /* 0x05 - 0x08 - coreboot Memory Console */
 	uint64_t	pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
 	uint64_t	gpei; /* 0x11 - 0x18 - GPE Wake Source */
 	uint64_t	nhla; /* 0x19 - 0x20 - NHLT Address */
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index 1654cd8..0f6d480 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -40,5 +40,5 @@
 	Offset (0x30),
 	,	 32,	/* 0x30 - CBMEM TOC */
 	,	 32,	/* 0x34 - Top of Low Memory */
-	CBMC,	 32,	/* 0x38 - coreboot mem console pointer */
+	,	 32,	/* 0x38 - coreboot mem console pointer */
 }
diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index 35308cd..5652761 100644
--- a/src/soc/intel/baytrail/include/soc/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -42,7 +42,7 @@
 	/* Base Addresses */
 	u32	obsolete_cmem; /* 0x30 - CBMEM TOC */
 	u32	tolm; /* 0x34 - Top of Low Memory */
-	u32	cbmc; /* 0x38 - coreboot memconsole */
+	u32	unused_was_cbmc; /* 0x38 - coreboot memconsole */
 };
 
 #endif /* _BAYTRAIL_NVS_H_ */
diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl
index c0839e6..fb28acc 100644
--- a/src/soc/intel/braswell/acpi/globalnvs.asl
+++ b/src/soc/intel/braswell/acpi/globalnvs.asl
@@ -41,5 +41,5 @@
 	Offset (0x30),
 	,	 32,	/* 0x30 - CBMEM TOC */
 	,	 32,	/* 0x34 - Top of Low Memory */
-	CBMC,	 32,	/* 0x38 - coreboot mem console pointer */
+	,	 32,	/* 0x38 - coreboot mem console pointer */
 }
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 59c6052..2351978 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -43,7 +43,7 @@
 	/* Base Addresses */
 	u32	obsolete_cmem; /* 0x30 - CBMEM TOC */
 	u32	tolm; /* 0x34 - Top of Low Memory */
-	u32	cbmc; /* 0x38 - coreboot memconsole */
+	u32	unused_was_cbmc; /* 0x38 - coreboot memconsole */
 };
 
 #endif /* _SOC_NVS_H_ */
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index c57a698..f627c80 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -31,7 +31,7 @@
 	u8	lids; /* 0x16 - LID State */
 	u8	unused_was_pwrs; /* 0x17 - AC Power State */
 	u32	obsolete_cmem; /* 0x18 - 0x1b - CBMEM TOC */
-	u32	cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
+	u32	unused_was_cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
 	u64	pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
 	u64	gpei; /* 0x28 - 0x2f - GPE wake status bit */
 };
diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
index bfc22fb..67fdbee 100644
--- a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
+++ b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
@@ -29,7 +29,7 @@
 	LIDS,	8,	// 0x16 - LID State
 	,	8,	// 0x17 - AC Power State
 	,	32,	// 0x18 - 0x1b - CBMEM TOC
-	CBMC,	32,	// 0x1c - 0x1f - coreboot Memory Console
+	,	32,	// 0x1c - 0x1f - coreboot Memory Console
 	PM1I,	64,	// 0x20 - 0x27 - PM1 wake status bit
 	GPEI,	64,	// 0x28 - 0x2f - GPE wake status bit
 }
diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
index 2c72b7d..adda519 100644
--- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
+++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
@@ -12,7 +12,7 @@
 	TLVL,	8,	// 0x05 - Throttle Level Limit
 	LIDS,	8,	// 0x06 - LID State
 	,	8,	// 0x07 - AC Power State
-	CBMC,	32,	// 0x08 - 0x0b AC Power State
+	,	32,	// 0x08 - 0x0b AC Power State
 	PM1I,	64,	// 0x0c - 0x13 PM1 wake status bit
 	GPEI,	64,	// 0x14 - 0x17 GPE wake status bit
 	DPTE,	8,	// 0x1c - Enable DPTF
diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h
index 4fc5b4c..071be66 100644
--- a/src/soc/intel/common/block/include/intelblocks/nvs.h
+++ b/src/soc/intel/common/block/include/intelblocks/nvs.h
@@ -14,7 +14,7 @@
 	u8	tlvl; /* 0x05 - Throttle Level Limit */
 	u8	lids; /* 0x06 - LID State */
 	u8	unused_was_pwrs; /* 0x07 - AC Power State */
-	u32	cbmc; /* 0x08 - 0xb coreboot Memory Console */
+	u32	unused_was_cbmc; /* 0x08 - 0xb coreboot Memory Console */
 	u64	pm1i; /* 0x0c - 0x13 PM1 wake status bit */
 	u64	gpei; /* 0x14 - 0x1b GPE wake status bit */
 	u8	dpte; /* 0x1c - Enable DPTF */
diff --git a/src/soc/intel/denverton_ns/acpi/globalnvs.asl b/src/soc/intel/denverton_ns/acpi/globalnvs.asl
index 3100c1f..9f19d25 100644
--- a/src/soc/intel/denverton_ns/acpi/globalnvs.asl
+++ b/src/soc/intel/denverton_ns/acpi/globalnvs.asl
@@ -38,7 +38,7 @@
 	Offset (0x30),
 	,	 32,	// 0x30 - CBMEM TOC
 	TOLM,	 32,	// 0x34 - Top of Low Memory
-	CBMC,	 32,	// 0x38 - coreboot mem console pointer
+	,	 32,	// 0x38 - coreboot mem console pointer
 	MMOB,	 32,	// 0x3c - MMIO Base Low Base
 	MMOL,	 32,	// 0x40 - MMIO Base Low Limit
 	MMHB,	 64,	// 0x44 - MMIO Base High Base
diff --git a/src/soc/intel/denverton_ns/include/soc/nvs.h b/src/soc/intel/denverton_ns/include/soc/nvs.h
index 5fa235e..65de751 100644
--- a/src/soc/intel/denverton_ns/include/soc/nvs.h
+++ b/src/soc/intel/denverton_ns/include/soc/nvs.h
@@ -38,7 +38,7 @@
 	/* Base Addresses */
 	u32 obsolete_cmem; /* 0x30 - CBMEM TOC */
 	u32 tolm;	  /* 0x34 - Top of Low Memory */
-	u32 cbmc;	  /* 0x38 - coreboot memconsole */
+	u32 unused_was_cbmc;	  /* 0x38 - coreboot memconsole */
 	u32 mmiob;	 /* 0x3c - MMIO Base Low */
 	u32 mmiol;	 /* 0x40 - MMIO Base Limit */
 	u64 mmiohb;	/* 0x44 - MMIO Base High */
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
index 8c9813e..bf9df69 100644
--- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
@@ -103,7 +103,7 @@
 
 	Offset (0xf5),
 	TPIQ,	 8,	// 0xf5 - trackpad IRQ value
-	CBMC,	32,
+	,	32,
 }
 
 External (\_TZ.SKIN)
diff --git a/src/southbridge/intel/bd82x6x/include/soc/nvs.h b/src/southbridge/intel/bd82x6x/include/soc/nvs.h
index 18f004a..86a8b10 100644
--- a/src/southbridge/intel/bd82x6x/include/soc/nvs.h
+++ b/src/southbridge/intel/bd82x6x/include/soc/nvs.h
@@ -104,7 +104,7 @@
 	u8	rsvd12[57];
 
 	u8	tpiq; /* 0xf5 - trackpad IRQ value */
-	u32     cbmc;
+	u32     unused_was_cbmc;
 };
 
 #endif /* SOUTHBRIDGE_INTEL_BD82X6X_NVS_H */
diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
index d9318c3..c14421c 100644
--- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
@@ -98,7 +98,7 @@
 	Offset (0xf0),
 	DOCK,	 8,	// 0xf0 - Docking Status
 	BTEN,	 8,	// 0xf1 - Bluetooth Enable
-	CBMC,	32,
+	,	32,
 	PM1I,	32,	// System Wake Source - PM1 Index
 	GPEI,	32,	// GPE Wake Source
 }
diff --git a/src/southbridge/intel/i82801gx/include/soc/nvs.h b/src/southbridge/intel/i82801gx/include/soc/nvs.h
index 54e4832..8e8c0a1 100644
--- a/src/southbridge/intel/i82801gx/include/soc/nvs.h
+++ b/src/southbridge/intel/i82801gx/include/soc/nvs.h
@@ -97,7 +97,7 @@
 	u8	dock; /* 0xf0 - Docking Status */
 	u8	bten;
 
-	u32     cbmc;
+	u32     unused_was_cbmc;
 
 	/* Required for future unified acpi_save_wake_source. */
 	u32	pm1i;
diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
index e2209e6..7e891c9 100644
--- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
@@ -100,7 +100,7 @@
 	Offset (0xf0),
 	DOCK,	 8,	// 0xf0 - Docking Status
 	BTEN,	 8,	// 0xf1 - Bluetooth Enable
-	CBMC,	32,
+	,	32,
 	PM1I,	32,	// System Wake Source - PM1 Index
 	GPEI,	32,	// GPE Wake Source
 
diff --git a/src/southbridge/intel/i82801ix/include/soc/nvs.h b/src/southbridge/intel/i82801ix/include/soc/nvs.h
index af3f1d3..fd136ba 100644
--- a/src/southbridge/intel/i82801ix/include/soc/nvs.h
+++ b/src/southbridge/intel/i82801ix/include/soc/nvs.h
@@ -97,7 +97,7 @@
 	u8	dock; /* 0xf0 - Docking Status */
 	u8	bten;
 
-	u32     cbmc;
+	u32     unused_was_cbmc;
 
 	/* Required for future unified acpi_save_wake_source. */
 	u32	pm1i;
diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
index 754b161..01a4d9b 100644
--- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
@@ -90,7 +90,7 @@
 	S7B1,	32,	// 0x9c - D23:F0 Serial IO SDIO BAR1
 
 	Offset (0xa0),
-	CBMC, 32,	// 0xa0 - coreboot mem console pointer
+	,	32,	// 0xa0 - coreboot mem console pointer
 
 	PM1I,	32,	// System Wake Source - PM1 Index
 	GPEI,	32,	// GPE Wake Source
diff --git a/src/southbridge/intel/lynxpoint/include/soc/nvs.h b/src/southbridge/intel/lynxpoint/include/soc/nvs.h
index 1996eba..3fe1ee7 100644
--- a/src/southbridge/intel/lynxpoint/include/soc/nvs.h
+++ b/src/southbridge/intel/lynxpoint/include/soc/nvs.h
@@ -72,7 +72,7 @@
 	/* LynxPoint Serial IO device BARs */
 	u32	s0b[8]; /* 0x60 - 0x7f - BAR0 */
 	u32	s1b[8]; /* 0x80 - 0x9f - BAR1 */
-	u32	cbmc;   /* 0xa0 - 0xa3 - coreboot memconsole */
+	u32	unused_was_cbmc;   /* 0xa0 - 0xa3 - coreboot memconsole */
 
 	/* Required for future unified acpi_save_wake_source. */
 	u32	pm1i;