intel/apollolake: Update gnvs for dptf
This patch updates dptf variable in gnvs based on device
configuration by reading the device tree structure.
BUG=chrome-os-partner:53096
TEST=Verify that the thermal zones are enumerated
under /sys/class/thermal in Amenia and Reef board.
Navigate to /sys/class/thermal, and verify that a
thermal zone of type TCPU exists there.
Change-Id: I8ab34cdc94d8cdc840b02347569a9f07688e92cd
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15620
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index a38c377..262e140 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -27,6 +27,8 @@
#include <soc/iomap.h>
#include <soc/pm.h>
#include <soc/nvs.h>
+#include <soc/pci_devs.h>
+#include "chip.h"
#define CSTATE_RES(address_space, width, offset, address) \
{ \
@@ -146,6 +148,15 @@
static void acpi_create_gnvs(struct global_nvs_t *gnvs)
{
+ struct soc_intel_apollolake_config *cfg;
+ struct device *dev = NB_DEV_ROOT;
+
+ if (!dev || !dev->chip_info) {
+ printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
+ return;
+ }
+ cfg = dev->chip_info;
+
if (IS_ENABLED(CONFIG_CONSOLE_CBMEM))
gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
@@ -154,6 +165,9 @@
chromeos_init_vboot(&gnvs->chromeos);
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
+
+ /* Enable DPTF based on mainboard configuration */
+ gnvs->dpte = cfg->dptf_enable;
}
void southbridge_inject_dsdt(device_t device)
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index a1df481..37b1cc0 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -102,6 +102,9 @@
/* Configure LPSS S0ix Enable */
uint8_t lpss_s0ix_enable;
+
+ /* Enable DPTF support */
+ int dptf_enable;
};
#endif /* _SOC_APOLLOLAKE_CHIP_H_ */