diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index b4041ef..00b3866 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -23,13 +23,13 @@
 #include <pc80/isa-dma.h>
 #include <pc80/mc146818rtc.h>
 #include <arch/ioapic.h>
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
 #include <arch/acpi.h>
 #include <arch/acpigen.h>
 #endif
 #include "i82371eb.h"
 
-#if IS_ENABLED(CONFIG_IOAPIC)
+#if CONFIG(IOAPIC)
 static void enable_intel_82093aa_ioapic(void)
 {
 	u16 reg16;
@@ -85,7 +85,7 @@
 	/* Initialize ISA DMA. */
 	isa_dma_init();
 
-#if IS_ENABLED(CONFIG_IOAPIC)
+#if CONFIG(IOAPIC)
 	/*
 	 * Unlike most other southbridges the 82371EB doesn't have a built-in
 	 * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs
@@ -116,7 +116,7 @@
 	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
 		IORESOURCE_RESERVE;
 
-#if IS_ENABLED(CONFIG_IOAPIC)
+#if CONFIG(IOAPIC)
 	res = new_resource(dev, 3); /* IOAPIC */
 	res->base = IO_APIC_ADDR;
 	res->size = 0x00001000;
@@ -125,7 +125,7 @@
 #endif
 }
 
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
 static void southbridge_acpi_fill_ssdt_generator(struct device *device)
 {
 	acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");
@@ -137,7 +137,7 @@
 	.read_resources		= sb_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
 	.write_acpi_tables      = acpi_write_hpet,
 	.acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator,
 #endif