coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c
index 110d67d..f16ee20 100644
--- a/src/soc/intel/denverton_ns/bootblock/bootblock.c
+++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c
@@ -58,13 +58,13 @@
void bootblock_soc_early_init(void)
{
-#if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
+#if (CONFIG(CONSOLE_SERIAL))
early_uart_init();
#endif
};
void bootblock_soc_init(void)
{
- if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE))
+ if (CONFIG(BOOTBLOCK_CONSOLE))
printk(BIOS_DEBUG, "FSP TempRamInit successful...\n");
};
diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c
index 955bf4b..baa0878 100644
--- a/src/soc/intel/denverton_ns/bootblock/uart.c
+++ b/src/soc/intel/denverton_ns/bootblock/uart.c
@@ -41,7 +41,7 @@
reg16 = pci_read_config16(uart_dev, PCI_BASE_ADDRESS_0) | mmio_base;
pci_write_config16(uart_dev, PCI_BASE_ADDRESS_0, reg16);
-#if (IS_ENABLED(CONFIG_NON_LEGACY_UART_MODE))
+#if (CONFIG(NON_LEGACY_UART_MODE))
/* Decode MMIO at MEMBA (BAR1) */
pci_write_config32(uart_dev, PCI_BASE_ADDRESS_1,
CONFIG_CONSOLE_UART_BASE_ADDRESS +
@@ -53,12 +53,12 @@
*/
pci_write_config16(uart_dev, PCI_COMMAND,
pci_read_config16(uart_dev, PCI_COMMAND) |
-#if (IS_ENABLED(CONFIG_NON_LEGACY_UART_MODE))
+#if (CONFIG(NON_LEGACY_UART_MODE))
PCI_COMMAND_MEMORY |
#endif
PCI_COMMAND_MASTER | PCI_COMMAND_IO);
-#if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_230400))
+#if (CONFIG(CONSOLE_SERIAL_230400))
/* Change the highest speed to 230400 */
uint32_t *psr_reg =
(uint32_t *)(CONFIG_CONSOLE_UART_BASE_ADDRESS +