coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c
index 0027744..e311ae6 100644
--- a/src/soc/intel/common/block/acpi/acpi.c
+++ b/src/soc/intel/common/block/acpi/acpi.c
@@ -180,7 +180,7 @@
return generic_pm1_en;
}
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE)
+#if CONFIG(SOC_INTEL_COMMON_ACPI_WAKE_SOURCE)
/*
* Save wake source information for calculating ACPI _SWS values
*
@@ -452,7 +452,7 @@
acpigen_write_processor_cnot(cores_per_package);
}
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE)
+#if CONFIG(SOC_INTEL_COMMON_ACPI_WAKE_SOURCE)
/* Save wake source data for ACPI _SWS methods in NVS */
static void acpi_save_wake_source(void *unused)
{
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 17b8dc0..d3ee671 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -167,11 +167,11 @@
invd
mov %eax, %cr0
-#if IS_ENABLED(CONFIG_INTEL_CAR_NEM)
+#if CONFIG(INTEL_CAR_NEM)
jmp car_nem
-#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS)
+#elif CONFIG(INTEL_CAR_CQOS)
jmp car_cqos
-#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED)
+#elif CONFIG(INTEL_CAR_NEM_ENHANCED)
jmp car_nem_enhanced
#else
jmp .halt_forever /* In case nothing has selected */
@@ -221,7 +221,7 @@
.word MTRR_FIX_4K_F8000
fixed_mtrr_list_size = . - fixed_mtrr_list
-#if IS_ENABLED(CONFIG_INTEL_CAR_NEM)
+#if CONFIG(INTEL_CAR_NEM)
.global car_nem
car_nem:
/* Disable cache eviction (setup stage) */
@@ -252,7 +252,7 @@
jmp car_init_done
-#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS)
+#elif CONFIG(INTEL_CAR_CQOS)
.global car_cqos
car_cqos:
/*
@@ -356,7 +356,7 @@
jmp car_init_done
-#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED)
+#elif CONFIG(INTEL_CAR_NEM_ENHANCED)
.global car_nem_enhanced
car_nem_enhanced:
/* Disable cache eviction (setup stage) */
diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S
index a4d16e8..ab7886c 100644
--- a/src/soc/intel/common/block/cpu/car/exit_car.S
+++ b/src/soc/intel/common/block/cpu/car/exit_car.S
@@ -23,7 +23,7 @@
.global chipset_teardown_car
chipset_teardown_car:
-#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)
+#if CONFIG(PAGING_IN_CACHE_AS_RAM)
/*
* Since Page table is located in CAR, disable paging before CAR
* teardown. Also clear CR3 and CR4.PAE.
@@ -50,7 +50,7 @@
and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax
wrmsr
-#if IS_ENABLED(CONFIG_INTEL_CAR_NEM)
+#if CONFIG(INTEL_CAR_NEM)
.global car_nem_teardown
car_nem_teardown:
@@ -65,7 +65,7 @@
and $(~(1 << 0)), %eax
wrmsr
-#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS)
+#elif CONFIG(INTEL_CAR_CQOS)
.global car_cqos_teardown
car_cqos_teardown:
@@ -86,7 +86,7 @@
and $~IA32_PQR_ASSOC_MASK, %edx
wrmsr
-#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED)
+#elif CONFIG(INTEL_CAR_NEM_ENHANCED)
.global car_nem_enhanced_teardown
car_nem_enhanced_teardown:
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index d196f61..2e3b99e 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -157,7 +157,7 @@
void *spibar = fast_spi_get_bar();
uint16_t hsfs = SPIBAR_HSFSTS_FLOCKDN;
- if (IS_ENABLED(CONFIG_FAST_SPI_DISABLE_WRITE_STATUS))
+ if (CONFIG(FAST_SPI_DISABLE_WRITE_STATUS))
hsfs |= SPIBAR_HSFSTS_WRSDIS;
write16(spibar + SPIBAR_HSFSTS_CTL, hsfs);
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c
index d77e052..0065a6c 100644
--- a/src/soc/intel/common/block/gpio/gpio.c
+++ b/src/soc/intel/common/block/gpio/gpio.c
@@ -35,7 +35,7 @@
PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK | \
PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK)
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL)
#define PAD_DW1_MASK (PAD_CFG1_IOSTERM_MASK | \
PAD_CFG1_PULL_MASK | \
PAD_CFG1_TOL_MASK | \
@@ -190,7 +190,7 @@
if (ENV_SMM)
return;
- if (!IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG))
+ if (!CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG))
return;
int irq;
@@ -276,7 +276,7 @@
/* Patch GPIO settings for SoC specifically */
soc_pad_conf = soc_gpio_pad_config_fixup(cfg, i, soc_pad_conf);
- if (IS_ENABLED(CONFIG_DEBUG_GPIO))
+ if (CONFIG(DEBUG_GPIO))
printk(BIOS_DEBUG,
"gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x"
" : 0x%08x]\n",
@@ -411,7 +411,7 @@
const struct pad_community *comm;
size_t group, pin;
- if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES))
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES))
return relative_pad_in_comm(gpio_get_community(gpio_num),
gpio_num);
@@ -489,7 +489,7 @@
comm++;
}
- if (IS_ENABLED(CONFIG_DEBUG_SMI))
+ if (CONFIG(DEBUG_SMI))
print_gpi_status(sts);
}
@@ -560,7 +560,7 @@
MISCCFG_GPE0_DW1_MASK |
MISCCFG_GPE0_DW0_MASK);
- if (IS_ENABLED(CONFIG_DEBUG_GPIO))
+ if (CONFIG(DEBUG_GPIO))
printk(BIOS_DEBUG, "misccfg_mask:%x misccfg_value:%x\n",
misccfg_mask, misccfg_value);
comm = soc_gpio_get_community(&gpio_communities);
diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c
index 3e58d60..81eb7ee 100644
--- a/src/soc/intel/common/block/gspi/gspi.c
+++ b/src/soc/intel/common/block/gspi/gspi.c
@@ -355,7 +355,7 @@
static uint32_t gspi_csctrl_state(uint32_t pol, enum cs_assert cs_assert)
{
- if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2))
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2))
return gspi_csctrl_state_v2(pol, cs_assert);
return gspi_csctrl_state_v1(pol, cs_assert);
@@ -379,7 +379,7 @@
static uint32_t gspi_csctrl_polarity(enum spi_polarity active_pol)
{
- if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2))
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2))
return gspi_csctrl_polarity_v2(active_pol);
return gspi_csctrl_polarity_v1(active_pol);
diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c
index 376a40d..8ab835e 100644
--- a/src/soc/intel/common/block/hda/hda.c
+++ b/src/soc/intel/common/block/hda/hda.c
@@ -23,7 +23,7 @@
#include <soc/intel/common/hda_verb.h>
#include <soc/ramstage.h>
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_HDA_VERB)
static void codecs_init(uint8_t *base, u32 codec_mask)
{
int i;
@@ -65,7 +65,7 @@
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_HDA_VERB)
.init = hda_init,
#endif
.ops_pci = &pci_dev_ops_pci,
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
index 35f89c9..0ad3e5c 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
@@ -76,7 +76,7 @@
#define PAD_CFG1_PULL_UP_20K (0xc << 10)
#define PAD_CFG1_PULL_UP_667 (0xd << 10)
#define PAD_CFG1_PULL_NATIVE (0xf << 10)
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY)
/* Tx enabled driving last value driven, Rx enabled */
#define PAD_CFG1_IOSSTATE_TxLASTRxE (0x0 << 14)
/* Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller
@@ -125,7 +125,7 @@
#define PAD_CFG2_DEBOUNCE_MASK 0x1f
/* voltage tolerance 0=3.3V default 1=1.8V tolerant */
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL)
#define PAD_CFG1_TOL_MASK (0x1 << 25)
#define PAD_CFG1_TOL_1V8 (0x1 << 25)
#endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL */
@@ -134,7 +134,7 @@
#define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value
#define PAD_PULL(value) PAD_CFG1_PULL_##value
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY)
#define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value
#define PAD_IOSTERM(value) PAD_CFG1_IOSTERM_##value
#else
@@ -147,7 +147,7 @@
PAD_CFG0_TRIG_##trig | \
PAD_CFG0_RX_POL_##inv)
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT)
#define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \
(PAD_CFG0_ROUTE_##route1 | \
PAD_CFG0_ROUTE_##route2 | \
@@ -180,7 +180,7 @@
_PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
PAD_IOSSTATE(TxLASTRxE))
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL)
/* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S
Not applicable to all SOCs. Refer EDS
*/
@@ -269,7 +269,7 @@
*/
#define PAD_NC(pad, pull) PAD_CFG_GPI(pad, pull, DEEP)
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS)
#define PAD_CFG_GPI_APIC(pad, pull, rst) \
_PAD_CFG_STRUCT(pad, \
@@ -384,7 +384,7 @@
PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \
PAD_IOSSTATE(TxDRxE))
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT)
#define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \
_PAD_CFG_STRUCT(pad, \
PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index 494a1b0..b383637 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -240,7 +240,7 @@
uint16_t com_enable = LPC_IOE_COMA_EN;
/* ComB Range 2F8h-2FFh [6:4] */
- if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE)) {
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE)) {
com_ranges |= LPC_IOD_COMB_RANGE;
com_enable |= LPC_IOE_COMB_EN;
}
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index c191ad0..0a5e1bf 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -46,7 +46,7 @@
/* disable parity error response, enable ISA */
pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~1, 1<<2);
- if (IS_ENABLED(CONFIG_PCIE_DEBUG_INFO)) {
+ if (CONFIG(PCIE_DEBUG_INFO)) {
printk(BIOS_SPEW, " MBL = 0x%08x\n",
pci_read_config32(dev, PCI_MEMORY_BASE));
printk(BIOS_SPEW, " PMBL = 0x%08x\n",
diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c
index 61991c2..4a35a03 100644
--- a/src/soc/intel/common/block/pcr/pcr.c
+++ b/src/soc/intel/common/block/pcr/pcr.c
@@ -25,7 +25,7 @@
#error "PCR_BASE_ADDRESS need to be non-zero!"
#endif
-#if !IS_ENABLED(CONFIG_PCR_COMMON_IOSF_1_0)
+#if !CONFIG(PCR_COMMON_IOSF_1_0)
#define PCR_SBI_CMD_TIMEOUT 10 /* 10ms */
@@ -76,7 +76,7 @@
void *pcr_reg_address(uint8_t pid, uint16_t offset)
{
- if (IS_ENABLED(CONFIG_PCR_COMMON_IOSF_1_0))
+ if (CONFIG(PCR_COMMON_IOSF_1_0))
assert(IS_ALIGNED(offset, sizeof(uint32_t)));
return __pcr_reg_address(pid, offset);
@@ -91,7 +91,7 @@
*/
static inline void check_pcr_offset_align(uint16_t offset, size_t size)
{
- const size_t align = IS_ENABLED(CONFIG_PCR_COMMON_IOSF_1_0) ?
+ const size_t align = CONFIG(PCR_COMMON_IOSF_1_0) ?
sizeof(uint32_t) : size;
assert(IS_ALIGNED(offset, align));
@@ -219,7 +219,7 @@
pcr_write8(pid, offset, data8);
}
-#if !IS_ENABLED(CONFIG_PCR_COMMON_IOSF_1_0)
+#if !CONFIG(PCR_COMMON_IOSF_1_0)
#ifdef __SIMPLE_DEVICE__
static int pcr_wait_for_completion(pci_devfn_t dev)
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c
index 1f25d75..43543a1 100644
--- a/src/soc/intel/common/block/pmc/pmc.c
+++ b/src/soc/intel/common/block/pmc/pmc.c
@@ -66,7 +66,7 @@
cfg->abase_addr, cfg->abase_size,
IORESOURCE_IO | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED);
- if (IS_ENABLED(CONFIG_PMC_INVALID_READ_AFTER_WRITE)) {
+ if (CONFIG(PMC_INVALID_READ_AFTER_WRITE)) {
/*
* The ACPI IO BAR (offset 0x20) is not PCI compliant. We've
* observed cases where the BAR reads back as 0, but the IO
@@ -105,7 +105,7 @@
void pmc_set_acpi_mode(void)
{
- if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
+ if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_DISABLE, APM_CNT);
printk(BIOS_DEBUG, "done.\n");
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index 6c967ad..f58d362 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -384,7 +384,7 @@
if (ps->pm1_sts & WAK_STS) {
switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
case ACPI_S3:
- if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
+ if (CONFIG(HAVE_ACPI_RESUME))
prev_sleep_state = ACPI_S3;
break;
case ACPI_S5:
@@ -432,7 +432,7 @@
return ps->prev_sleep_state;
}
-#if IS_ENABLED(CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK)
+#if CONFIG(PMC_GLOBAL_RESET_ENABLE_LOCK)
/*
* If possible, lock 0xcf9. Once the register is locked, it can't be changed.
* This lock is reset on cold boot, hard reset, soft reset and Sx.
diff --git a/src/soc/intel/common/block/rtc/rtc.c b/src/soc/intel/common/block/rtc/rtc.c
index 2d70de2..5a0d45c 100644
--- a/src/soc/intel/common/block/rtc/rtc.c
+++ b/src/soc/intel/common/block/rtc/rtc.c
@@ -53,7 +53,7 @@
PCR_RTC_CONF_BILD);
}
-#if IS_ENABLED(CONFIG_INTEL_HAS_TOP_SWAP)
+#if CONFIG(INTEL_HAS_TOP_SWAP)
void configure_rtc_buc_top_swap(enum ts_config ts_state)
{
pcr_rmw32(PID_RTC, PCR_RTC_BUC, ~PCR_RTC_BUC_TOP_SWAP, ts_state);
diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c
index 4c32520..0801cb7 100644
--- a/src/soc/intel/common/block/sata/sata.c
+++ b/src/soc/intel/common/block/sata/sata.c
@@ -52,7 +52,7 @@
/* Read Ports Implemented (GHC_PI) */
port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED);
- if (IS_ENABLED(CONFIG_SOC_AHCI_PORT_IMPLEMENTED_INVERT))
+ if (CONFIG(SOC_AHCI_PORT_IMPLEMENTED_INVERT))
port_impl = ~port_impl;
port_impl &= 0x07; /* bit 0-2 */
diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c
index ea8d1b0..2794a3b 100644
--- a/src/soc/intel/common/block/scs/sd.c
+++ b/src/soc/intel/common/block/scs/sd.c
@@ -19,7 +19,7 @@
#include <device/pci_ids.h>
#include <intelblocks/sd.h>
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
static void sd_fill_ssdt(struct device *dev)
{
const char *path;
@@ -59,7 +59,7 @@
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
.acpi_fill_ssdt_generator = sd_fill_ssdt,
#endif
.ops_pci = &pci_dev_ops_pci,
diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c
index f1a2ca0..1a215eb 100644
--- a/src/soc/intel/common/block/smbus/tco.c
+++ b/src/soc/intel/common/block/smbus/tco.c
@@ -133,7 +133,7 @@
*/
void tco_configure(void)
{
- if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS))
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS))
tco_enable_bar();
tco_timer_disable();
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index 0c10d6b..16bb3a2 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -192,7 +192,7 @@
mainboard_smi_sleep(slp_typ);
/* Log S3, S4, and S5 entry */
- if (slp_typ >= ACPI_S3 && IS_ENABLED(CONFIG_ELOG_GSMI))
+ if (slp_typ >= ACPI_S3 && CONFIG(ELOG_GSMI))
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
/* Clear pending GPE events */
@@ -324,7 +324,7 @@
}
finalize_done = 1;
- if (IS_ENABLED(CONFIG_SPI_FLASH_SMM))
+ if (CONFIG(SPI_FLASH_SMM))
/* Re-init SPI driver to handle locked BAR */
fast_spi_init();
@@ -361,13 +361,13 @@
break;
case APM_CNT_ACPI_DISABLE:
pmc_disable_pm1_control(SCI_EN);
- if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS))
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS))
pmc_enable_smi(ESPI_SMI_EN);
printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
break;
case APM_CNT_ACPI_ENABLE:
pmc_enable_pm1_control(SCI_EN);
- if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS))
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS))
pmc_disable_smi(ESPI_SMI_EN);
printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
break;
@@ -387,11 +387,11 @@
}
break;
case APM_CNT_ELOG_GSMI:
- if (IS_ENABLED(CONFIG_ELOG_GSMI))
+ if (CONFIG(ELOG_GSMI))
southbridge_smi_gsmi(save_state_ops);
break;
case APM_CNT_SMMSTORE:
- if (IS_ENABLED(CONFIG_SMMSTORE))
+ if (CONFIG(SMMSTORE))
southbridge_smi_store(save_state_ops);
break;
case APM_CNT_FINALIZE:
@@ -414,7 +414,7 @@
*/
if ((pm1_sts & PWRBTN_STS) && (pm1_en & PWRBTN_EN)) {
/* power button pressed */
- if (IS_ENABLED(CONFIG_ELOG_GSMI))
+ if (CONFIG(ELOG_GSMI))
elog_add_event(ELOG_TYPE_POWER_BUTTON);
pmc_disable_pm1_control(-1UL);
pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c
index d929975..dd8bab3 100644
--- a/src/soc/intel/common/block/smm/smm.c
+++ b/src/soc/intel/common/block/smm/smm.c
@@ -95,7 +95,7 @@
*size = sa_get_tseg_size();
}
-#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS)
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS)
static void smm_disable_espi(void *dest)
{
pmc_disable_smi(ESPI_SMI_EN);
diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c
index c02cfed..85db5cf 100644
--- a/src/soc/intel/common/block/spi/spi.c
+++ b/src/soc/intel/common/block/spi/spi.c
@@ -26,7 +26,7 @@
const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
{ .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 },
-#if !ENV_SMM && IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI)
+#if !ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_GSPI)
{ .ctrlr = &gspi_ctrlr, .bus_start = 1,
.bus_end = 1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)},
#endif
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index f9782aa..d95a4eb 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -160,7 +160,7 @@
uintptr_t top_of_ram;
int index = *resource_count;
- if (IS_ENABLED(CONFIG_SA_ENABLE_DPR))
+ if (CONFIG(SA_ENABLE_DPR))
dpr_size = sa_get_dpr_size();
/* Get SoC reserve memory size as per user selection */
@@ -270,7 +270,7 @@
soc_add_fixed_mmio_resources(dev, &index);
/* Calculate and add DRAM resources. */
sa_add_dram_resources(dev, &index);
- if (IS_ENABLED(CONFIG_SA_ENABLE_IMR))
+ if (CONFIG(SA_ENABLE_IMR))
/* Add the isolated memory ranges (IMRs). */
sa_add_imr_resources(dev, &index);
}
@@ -292,7 +292,7 @@
.enable_resources = pci_dev_enable_resources,
.init = soc_systemagent_init,
.ops_pci = &pci_dev_ops_pci,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = sa_write_acpi_tables,
#endif
};
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index 7f105d7..7f21372 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -45,7 +45,7 @@
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL);
}
-#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)
+#if CONFIG(DRIVERS_UART_8250MEM)
uintptr_t uart_platform_base(int idx)
{
/* return Base address for UART console index */
@@ -92,7 +92,7 @@
* config option is not selected.
* By default return NULL in this case to avoid compilation errors.
*/
- if (!IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE))
+ if (!CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
return NULL;
int console_index = uart_get_valid_index();
@@ -141,7 +141,7 @@
uart_common_init(uart_get_device(),
UART_BASE(CONFIG_UART_FOR_CONSOLE));
- if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))
+ if (!CONFIG(DRIVERS_UART_8250MEM_32))
/* Put UART in byte access mode for 16550 compatibility */
soc_uart_set_legacy_mode();
@@ -156,7 +156,7 @@
pci_dev_read_resources(dev);
/* Set the configured UART base address for the debug port */
- if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE) &&
+ if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE) &&
uart_is_debug_controller(dev)) {
struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
/* Need to set the base and size for the resource allocator. */
@@ -204,7 +204,7 @@
* If coreboot has CONSOLE_SERIAL enabled, the skip re-initializing
* controller here.
*/
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
+ if (CONFIG(CONSOLE_SERIAL))
return false;
/* If this device does not correspond to debug port, then skip. */
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c
index f1bb935..c429e7d 100644
--- a/src/soc/intel/common/block/xhci/xhci.c
+++ b/src/soc/intel/common/block/xhci/xhci.c
@@ -29,7 +29,7 @@
.init = soc_xhci_init,
.ops_pci = &pci_dev_ops_pci,
.scan_bus = scan_usb_bus,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
.acpi_name = soc_acpi_name,
#endif
};