coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index 29f4274..c31cb70 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -424,7 +424,7 @@
}
-#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI)
+#if CONFIG(CONSOLE_VGA_MULTI)
extern struct device *vga_pri; // the primary vga device, defined in device.c
#endif
@@ -438,7 +438,7 @@
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI)
+#if CONFIG(CONSOLE_VGA_MULTI)
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
/* We need to make sure the vga_pri is under the link */
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index 9da4e8e..381d198 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -410,7 +410,7 @@
report_resource_stored(dev, resource, buf);
}
-#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI)
+#if CONFIG(CONSOLE_VGA_MULTI)
extern struct device *vga_pri; // the primary vga device, defined in device.c
#endif
@@ -424,7 +424,7 @@
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI)
+#if CONFIG(CONSOLE_VGA_MULTI)
printk(BIOS_DEBUG,
"VGA: vga_pri bus num = %d bus range [%d,%d]\n",
vga_pri->bus->secondary, link->secondary,
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index 7a75997..367feca 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -367,7 +367,7 @@
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
+#if CONFIG(MULTIPLE_VGA_ADAPTERS)
extern struct device *vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index ddfab82..44f49ea 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -366,7 +366,7 @@
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
+#if CONFIG(MULTIPLE_VGA_ADAPTERS)
extern struct device *vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c
index 9840c1c7..fea097f 100644
--- a/src/northbridge/amd/agesa/family16kb/state_machine.c
+++ b/src/northbridge/amd/agesa/family16kb/state_machine.c
@@ -32,7 +32,7 @@
{
AGESA_STATUS status;
- if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) {
+ if (CONFIG(ENABLE_MRC_CACHE)) {
status = OemInitResume(&Post->MemConfig.MemContext);
if (status == AGESA_SUCCESS)
Post->MemConfig.MemRestoreCtl = 1;
diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h
index 43b205a..93625fc 100644
--- a/src/northbridge/amd/agesa/state_machine.h
+++ b/src/northbridge/amd/agesa/state_machine.h
@@ -20,7 +20,7 @@
#include <AGESA.h>
#include <AMD.h>
-#define HAS_LEGACY_WRAPPER IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
+#define HAS_LEGACY_WRAPPER CONFIG(BINARYPI_LEGACY_WRAPPER)
/* eventlog */
const char *agesa_struct_name(int state);
@@ -30,7 +30,7 @@
/* For suspend-to-ram support. */
-#if !IS_ENABLED(CONFIG_CPU_AMD_PI)
+#if !CONFIG(CPU_AMD_PI)
/* TODO: With binaryPI we need different interface. */
AGESA_STATUS OemInitResume(AMD_S3_PARAMS *dataBlock);
AGESA_STATUS OemS3LateRestore(AMD_S3_PARAMS *dataBlock);
@@ -89,18 +89,18 @@
void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late);
void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late);
-#if IS_ENABLED(CONFIG_CPU_AMD_PI_00660F01)
+#if CONFIG(CPU_AMD_PI_00660F01)
typedef void AMD_S3SAVE_PARAMS;
#endif
void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save);
/* FCH callouts, not used with CIMx. */
#define HAS_AGESA_FCH_OEM_CALLOUT \
- IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) || \
- IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) || \
- IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) || \
- IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) || \
- IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
+ CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) || \
+ CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) || \
+ CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) || \
+ CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON) || \
+ CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
#if HAS_AGESA_FCH_OEM_CALLOUT
/* FIXME: Structures included here were supposed to be private to AGESA. */
diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c
index 405a700..5090352 100644
--- a/src/northbridge/amd/amdfam10/debug.c
+++ b/src/northbridge/amd/amdfam10/debug.c
@@ -22,7 +22,7 @@
void print_debug_addr(const char *str, void *val)
{
-#if IS_ENABLED(CONFIG_DEBUG_CAR)
+#if CONFIG(DEBUG_CAR)
printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val);
#endif
}
@@ -206,7 +206,7 @@
}
}
-#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
+#if CONFIG(DEBUG_SMBUS)
void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
@@ -300,17 +300,17 @@
}
}
-#if IS_ENABLED(CONFIG_DIMM_DDR2)
+#if CONFIG(DIMM_DDR2)
void print_tx(const char *strval, u32 val)
{
-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
+#if CONFIG(DEBUG_RAM_SETUP)
printk(BIOS_DEBUG, "%s%08x\n", strval, val);
#endif
}
void print_t(const char *strval)
{
-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
+#if CONFIG(DEBUG_RAM_SETUP)
printk(BIOS_DEBUG, "%s", strval);
#endif
}
@@ -318,7 +318,7 @@
void print_tf(const char *func, const char *strval)
{
-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
+#if CONFIG(DEBUG_RAM_SETUP)
printk(BIOS_DEBUG, "%s: %s", func, strval);
#endif
}
diff --git a/src/northbridge/amd/amdfam10/debug.h b/src/northbridge/amd/amdfam10/debug.h
index a23303e..3710d15 100644
--- a/src/northbridge/amd/amdfam10/debug.h
+++ b/src/northbridge/amd/amdfam10/debug.h
@@ -32,7 +32,7 @@
void dump_pci_devices(void);
void dump_pci_devices_on_bus(u32 busn);
-#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
+#if CONFIG(DEBUG_SMBUS)
void dump_spd_registers(const struct mem_controller *ctrl);
void dump_smbus_registers(void);
#endif
diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c
index afa07bb..d8784ac 100644
--- a/src/northbridge/amd/amdfam10/early_ht.c
+++ b/src/northbridge/amd/amdfam10/early_ht.c
@@ -22,7 +22,7 @@
// mmconf is not ready yet
void set_bsp_node_CHtExtNodeCfgEn(void)
{
-#if IS_ENABLED(CONFIG_EXT_RT_TBL_SUPPORT)
+#if CONFIG(EXT_RT_TBL_SUPPORT)
u32 dword;
dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68);
dword |= (1<<27) | (1<<25);
diff --git a/src/northbridge/amd/amdfam10/link_control.c b/src/northbridge/amd/amdfam10/link_control.c
index f82f238..871a436 100644
--- a/src/northbridge/amd/amdfam10/link_control.c
+++ b/src/northbridge/amd/amdfam10/link_control.c
@@ -74,7 +74,7 @@
enable_c_states = 0;
enable_cc6 = 0;
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
uint8_t nvram;
if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS)
diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c
index 8323c1e..bbaec53 100644
--- a/src/northbridge/amd/amdfam10/misc_control.c
+++ b/src/northbridge/amd/amdfam10/misc_control.c
@@ -153,7 +153,7 @@
printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. ");
-#if IS_ENABLED(CONFIG_DIMM_DDR3) && !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA)
+#if CONFIG(DIMM_DDR3) && !CONFIG(NORTHBRIDGE_AMD_AGESA)
uint8_t node;
uint8_t slot;
uint8_t dimm_present;
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index d202cd8..16b7bec 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -35,7 +35,7 @@
#include <cpu/amd/msr.h>
#include <cpu/amd/family_10h-family_15h/ram_calc.h>
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
#include <cpu/amd/multicore.h>
#include <pc80/mc146818rtc.h>
#endif
@@ -49,7 +49,7 @@
#include <cpu/amd/model_10xxx_rev.h>
#endif
-#if IS_ENABLED(CONFIG_DIMM_DDR3)
+#if CONFIG(DIMM_DDR3)
#include "../amdmct/mct_ddr3/s3utils.h"
#endif
@@ -316,7 +316,7 @@
{
struct bus *link;
-#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA)
+#if CONFIG(CPU_AMD_SOCKET_G34_NON_AGESA)
if (is_fam15h()) {
uint8_t current_link_number = 0;
@@ -361,7 +361,7 @@
for (link = dev->link_list; link; link = link->next) {
if (link->ht_link_up) {
- if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX))
+ if (CONFIG(CPU_AMD_MODEL_10XXX))
amd_g34_fixup(link, dev);
amdfam10_scan_chain(link);
}
@@ -581,7 +581,7 @@
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
+#if CONFIG(MULTIPLE_VGA_ADAPTERS)
extern struct device *vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
@@ -640,7 +640,7 @@
{
}
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
static const char *amdfam10_northbridge_acpi_name(const struct device *dev)
{
return "";
@@ -653,7 +653,7 @@
.enable_resources = pci_dev_enable_resources,
.init = mcf0_control_init,
.scan_bus = amdfam10_scan_chains,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = northbridge_write_acpi_tables,
.acpi_fill_ssdt_generator = northbridge_acpi_write_vars,
.acpi_name = amdfam10_northbridge_acpi_name,
@@ -886,7 +886,7 @@
static void setup_uma_memory(void)
{
-#if IS_ENABLED(CONFIG_GFXUMA)
+#if CONFIG(GFXUMA)
uint32_t topmem = (uint32_t) bsp_topmem();
uma_memory_size = get_uma_memory_size(topmem);
uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */
@@ -985,7 +985,7 @@
i, mmio_basek, basek, limitk);
}
-#if IS_ENABLED(CONFIG_GFXUMA)
+#if CONFIG(GFXUMA)
uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
#endif
@@ -1035,7 +1035,7 @@
}
}
-#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)
+#if CONFIG(GENERATE_SMBIOS_TABLES)
static int amdfam10_get_smbios_data16(int *count, int handle,
unsigned long *current)
{
@@ -1085,7 +1085,7 @@
static uint16_t amdmct_mct_speed_enum_to_mhz(uint8_t speed)
{
if (is_fam15h()) {
- if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
+ if (CONFIG(DIMM_DDR3)) {
switch (speed) {
case 0x4:
return 333;
@@ -1106,7 +1106,7 @@
return 0;
}
} else {
- if (IS_ENABLED(CONFIG_DIMM_DDR2)) {
+ if (CONFIG(DIMM_DDR2)) {
switch (speed) {
case 1:
return 200;
@@ -1121,7 +1121,7 @@
default:
return 0;
}
- } else if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
+ } else if (CONFIG(DIMM_DDR3)) {
switch (speed) {
case 3:
return 333;
@@ -1185,7 +1185,7 @@
cols = mem_info->dct_stat[node].DimmCols[slot];
ranks = mem_info->dct_stat[node].DimmRanks[slot];
banks = mem_info->dct_stat[node].DimmBanks[slot];
-#if IS_ENABLED(CONFIG_DIMM_DDR3)
+#if CONFIG(DIMM_DDR3)
chip_size = mem_info->dct_stat[node].DimmChipSize[slot];
chip_width = mem_info->dct_stat[node].DimmChipWidth[slot];
#else
@@ -1193,7 +1193,7 @@
chip_width = 0;
#endif
uint64_t dimm_size_bytes;
- if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
+ if (CONFIG(DIMM_DDR3)) {
width = mem_info->dct_stat[node].DimmWidth[slot];
dimm_size_bytes = ((width / chip_width) * chip_size * ranks) / 8;
} else {
@@ -1226,9 +1226,9 @@
snprintf(string_buffer, sizeof(string_buffer), "NODE %d DIMM_%s%d", node, (slot & 0x1)?"B":"A", (slot >> 1) + 1);
}
t->device_locator = smbios_add_string(t->eos, string_buffer);
- if (IS_ENABLED(CONFIG_DIMM_DDR2))
+ if (CONFIG(DIMM_DDR2))
t->memory_type = MEMORY_TYPE_DDR2;
- else if (IS_ENABLED(CONFIG_DIMM_DDR3))
+ else if (CONFIG(DIMM_DDR3))
t->memory_type = MEMORY_TYPE_DDR3;
t->type_detail = MEMORY_TYPE_DETAIL_SYNCHRONOUS;
if (mem_info->dct_stat[node].DimmRegistered[slot])
@@ -1245,13 +1245,13 @@
snprintf(string_buffer, sizeof(string_buffer), "%08X", mem_info->dct_stat[node].DimmSerialNumber[slot]);
t->serial_number = smbios_add_string(t->eos, string_buffer);
}
- if (IS_ENABLED(CONFIG_DIMM_DDR2)) {
+ if (CONFIG(DIMM_DDR2)) {
/* JEDEC specifies 1.8V only, so assume that the memory is configured for 1.8V */
t->minimum_voltage = 1800;
t->maximum_voltage = 1800;
t->configured_voltage = 1800;
- } else if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
-#if IS_ENABLED(CONFIG_DIMM_DDR3)
+ } else if (CONFIG(DIMM_DDR3)) {
+#if CONFIG(DIMM_DDR3)
/* Find the maximum and minimum supported voltages */
uint8_t supported_voltages = mem_info->dct_stat[node].DimmSupportedVoltages[slot];
uint8_t configured_voltage = mem_info->dct_stat[node].DimmConfiguredVoltage[slot];
@@ -1308,7 +1308,7 @@
}
#endif
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
static const char *amdfam10_domain_acpi_name(const struct device *dev)
{
if (dev->path.type == DEVICE_PATH_DOMAIN)
@@ -1324,10 +1324,10 @@
.enable_resources = NULL,
.init = NULL,
.scan_bus = amdfam10_domain_scan_bus,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
.acpi_name = amdfam10_domain_acpi_name,
#endif
-#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)
+#if CONFIG(GENERATE_SMBIOS_TABLES)
.get_smbios_data = amdfam10_get_smbios_data,
#endif
};
@@ -1356,7 +1356,7 @@
sysconf.bsp_apicid = lapicid();
sysconf.apicid_offset = sysconf.bsp_apicid;
-#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID)
+#if CONFIG(ENABLE_APIC_EXT_ID)
if (pci_read_config32(dev, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
{
sysconf.enabled_apic_ext_id = 1;
@@ -1451,7 +1451,7 @@
}
disable_siblings = !CONFIG_LOGICAL_CPUS;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
get_option(&disable_siblings, "multi_core");
#endif
@@ -1656,7 +1656,7 @@
}
}
-#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
+#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
if (sysconf.enabled_apic_ext_id) {
if (apic_id != 0 || sysconf.lift_bsp_apicid) {
apic_id += sysconf.apicid_offset;
@@ -1978,7 +1978,7 @@
}
static void root_complex_finalize(void *chip_info) {
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && IS_ENABLED(CONFIG_DIMM_DDR3)
+#if CONFIG(HAVE_ACPI_RESUME) && CONFIG(DIMM_DDR3)
save_mct_information_to_nvram();
#endif
}
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index 8dee9ab..4f31a5e 100644
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -150,8 +150,8 @@
uint8_t MaxDimmsInstallable = 2;
/* Return limited maximum RAM frequency */
- if (IS_ENABLED(CONFIG_DIMM_DDR2)) {
- if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) {
+ if (CONFIG(DIMM_DDR2)) {
+ if (CONFIG(DIMM_REGISTERED) && registered) {
/* K10 BKDG Rev. 3.62 Table 53 */
if (count > 2) {
/* Limit to DDR2-533 */
@@ -170,7 +170,7 @@
}
}
}
- } else if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
+ } else if (CONFIG(DIMM_DDR3)) {
if (voltage == 0) {
printk(BIOS_DEBUG, "%s: WARNING: Mainboard DDR3 voltage unknown, assuming 1.5V!\n", __func__);
voltage = 0x1;
@@ -179,7 +179,7 @@
if (is_fam15h()) {
if (CONFIG_CPU_SOCKET_TYPE == 0x15) {
/* Socket G34 */
- if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) {
+ if (CONFIG(DIMM_REGISTERED) && registered) {
/* Fam15h BKDG Rev. 3.14 Table 27 */
if (voltage & 0x4) {
/* 1.25V */
@@ -317,7 +317,7 @@
}
} else if (CONFIG_CPU_SOCKET_TYPE == 0x14) {
/* Socket C32 */
- if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) {
+ if (CONFIG(DIMM_REGISTERED) && registered) {
/* Fam15h BKDG Rev. 3.14 Table 30 */
if (voltage & 0x4) {
/* 1.25V */
@@ -486,7 +486,7 @@
*/
}
} else {
- if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) {
+ if (CONFIG(DIMM_REGISTERED) && registered) {
/* K10 BKDG Rev. 3.62 Table 34 */
if (count > 2) {
/* Limit to DDR3-800 */
@@ -548,7 +548,7 @@
}
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
u8 mctGetProcessorPackageType(void) {
/* FIXME: I guess this belongs wherever mctGetLogicalCPUID ends up ? */
u32 BrandId = cpuid_ebx(0x80000001);
@@ -601,7 +601,7 @@
mem_info->ecc_scrub_rate = mctGet_NVbits(NV_DramBKScrub);
/* Zero out invalid/unused pointers */
-#if IS_ENABLED(CONFIG_DIMM_DDR3)
+#if CONFIG(DIMM_DDR3)
for (i = 0; i < MAX_NODES_SUPPORTED; i++) {
mem_info->dct_stat[i].C_MCTPtr = NULL;
mem_info->dct_stat[i].C_DCTPtr[0] = NULL;
diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c
index f919335..8c33ad8 100644
--- a/src/northbridge/amd/amdht/h3finit.c
+++ b/src/northbridge/amd/amdht/h3finit.c
@@ -1489,13 +1489,13 @@
cbPCBFreqLimit = ht_speed_mhz_to_hw(pDat->HtBlock->ht_link_configuration->ht_speed_limit);
cbPCBFreqLimit = min(cbPCBFreqLimit, cbPCBFreqLimit_NVRAM);
-#if IS_ENABLED(CONFIG_LIMIT_HT_DOWN_WIDTH_8)
+#if CONFIG(LIMIT_HT_DOWN_WIDTH_8)
cbPCBABDownstreamWidth = 8;
#else
cbPCBABDownstreamWidth = 16;
#endif
-#if IS_ENABLED(CONFIG_LIMIT_HT_UP_WIDTH_8)
+#if CONFIG(LIMIT_HT_UP_WIDTH_8)
cbPCBBAUpstreamWidth = 8;
#else
cbPCBBAUpstreamWidth = 16;
diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c
index 6552be9..bad8993 100644
--- a/src/northbridge/amd/amdht/ht_wrapper.c
+++ b/src/northbridge/amd/amdht/ht_wrapper.c
@@ -272,7 +272,7 @@
*/
void amd_ht_fixup(struct sys_info *sysinfo) {
printk(BIOS_DEBUG, "%s\n", __func__);
- if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) {
+ if (CONFIG(CPU_AMD_MODEL_10XXX)) {
uint8_t rev_gte_d = 0;
uint8_t fam15h = 0;
uint8_t dual_node = 0;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 6f09b12..9178c78 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -2620,7 +2620,7 @@
mct_ForceNBPState0_En_Fam15(pMCTstat, pDCTstat);
}
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if CONFIG(HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DCT configuration from NVRAM\n");
if (restore_mct_information_from_nvram(0) != 0)
printk(BIOS_CRIT, "%s: ERROR: Unable to restore DCT configuration from NVRAM\n", __func__);
@@ -2692,11 +2692,11 @@
nvram = 0;
set_option("allow_spd_nvram_cache_restore", &nvram);
-#if IS_ENABLED(CONFIG_DIMM_VOLTAGE_SET_SUPPORT)
+#if CONFIG(DIMM_VOLTAGE_SET_SUPPORT)
printk(BIOS_DEBUG, "%s: DIMMSetVoltage\n", __func__);
DIMMSetVoltages(pMCTstat, pDCTstatA); /* Set the DIMM voltages (mainboard specific) */
#endif
- if (!IS_ENABLED(CONFIG_DIMM_VOLTAGE_SET_SUPPORT)) {
+ if (!CONFIG(DIMM_VOLTAGE_SET_SUPPORT)) {
/* Assume 1.5V operation */
for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
struct DCTStatStruc *pDCTstat;
@@ -3674,7 +3674,7 @@
mct_WriteLevelization_HW(pMCTstat, pDCTstatA, SecondPass);
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if CONFIG(HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DIMM training configuration from NVRAM\n");
if (restore_mct_information_from_nvram(1) != 0)
printk(BIOS_CRIT, "%s: ERROR: Unable to restore DCT configuration from NVRAM\n", __func__);
@@ -5836,7 +5836,7 @@
}
}
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if CONFIG(HAVE_ACPI_RESUME)
calculate_and_store_spd_hashes(pMCTstat, pDCTstat);
if (load_spd_hashes_from_nvram(pMCTstat, pDCTstat) < 0) {
@@ -5853,7 +5853,7 @@
if (get_option(&nvram, "allow_spd_nvram_cache_restore") == CB_SUCCESS)
allow_config_restore = !!nvram;
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if CONFIG(HAVE_ACPI_RESUME)
if (pMCTstat->nvram_checksum != calculate_nvram_mct_hash())
allow_config_restore = 0;
#else
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
index 7267f12..a78a752 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
@@ -536,7 +536,7 @@
data->f2x9cx0d0f812f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f812f);
/* Stage 11 */
- if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
+ if (CONFIG(DIMM_DDR3)) {
for (i = 0; i < 12; i++)
data->f2x9cx30[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x30 + i);
for (i = 0; i < 12; i++)
@@ -654,7 +654,7 @@
for (i = 0; i < 12; i++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x20 + i, data->f2x9cx20[i]);
- if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
+ if (CONFIG(DIMM_DDR3)) {
for (i = 0; i < 12; i++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x30 + i, data->f2x9cx30[i]);
for (i = 0; i < 12; i++)
@@ -1093,7 +1093,7 @@
}
/* Stage 11 */
- if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
+ if (CONFIG(DIMM_DDR3)) {
for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
for (channel = 0; channel < 2; channel++) {
struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h
index db92fa7..92dc0b8 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti.h
+++ b/src/northbridge/amd/amdmct/wrappers/mcti.h
@@ -56,7 +56,7 @@
#endif
#ifndef MAX_DIMMS_SUPPORTED
-#if IS_ENABLED(CONFIG_DIMM_DDR3)
+#if CONFIG(DIMM_DDR3)
#define MAX_DIMMS_SUPPORTED 6
#else
#define MAX_DIMMS_SUPPORTED 8
@@ -72,7 +72,7 @@
#endif
#ifndef MEM_MAX_LOAD_FREQ
-#if IS_ENABLED(CONFIG_DIMM_DDR3)
+#if CONFIG(DIMM_DDR3)
#define MEM_MAX_LOAD_FREQ 933
#define MEM_MIN_PLATFORM_FREQ_FAM10 400
#define MEM_MIN_PLATFORM_FREQ_FAM15 333
@@ -112,13 +112,13 @@
static const uint16_t ddr2_limits[4] = {400, 333, 266, 200};
static const uint16_t ddr3_limits[16] = {933, 800, 666, 533, 400, 333, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
-#if IS_ENABLED(CONFIG_DIMM_DDR3)
+#if CONFIG(DIMM_DDR3)
#include <northbridge/amd/amdmct/mct_ddr3/mct_d.h>
#else
#include <northbridge/amd/amdmct/mct/mct_d.h>
#endif
-#if IS_ENABLED(CONFIG_DIMM_DDR2)
+#if CONFIG(DIMM_DDR2)
void mctSaveDQSSigTmg_D(void);
void mctGetDQSSigTmg_D(void);
u8 mctSetNodeBoundary_D(void);
@@ -144,7 +144,7 @@
void mctHookAfterAnyTraining(void);
uint64_t mctGetLogicalCPUID_D(u8 node);
-#if IS_ENABLED(CONFIG_DIMM_DDR3)
+#if CONFIG(DIMM_DDR3)
void vErratum372(struct DCTStatStruc *pDCTstat);
void vErratum414(struct DCTStatStruc *pDCTstat);
u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val);
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index b7d2476..e42085d 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -102,9 +102,9 @@
if (get_option(&nvram, "max_mem_clock") == CB_SUCCESS) {
int limit = val;
- if (IS_ENABLED(CONFIG_DIMM_DDR3))
+ if (CONFIG(DIMM_DDR3))
limit = ddr3_limits[nvram & 0xf];
- else if (IS_ENABLED(CONFIG_DIMM_DDR2))
+ else if (CONFIG(DIMM_DDR2))
limit = ddr2_limits[nvram & 0x3];
val = min(limit, val);
}
@@ -130,16 +130,16 @@
//val = 2; /* S4 (Unbuffered SO-DIMMS) */
break;
case NV_BYPMAX:
-#if !IS_ENABLED(CONFIG_GFXUMA)
+#if !CONFIG(GFXUMA)
val = 4;
-#elif IS_ENABLED(CONFIG_GFXUMA)
+#elif CONFIG(GFXUMA)
val = 7;
#endif
break;
case NV_RDWRQBYP:
-#if !IS_ENABLED(CONFIG_GFXUMA)
+#if !CONFIG(GFXUMA)
val = 2;
-#elif IS_ENABLED(CONFIG_GFXUMA)
+#elif CONFIG(GFXUMA)
val = 3;
#endif
break;
@@ -193,9 +193,9 @@
val = !!nvram;
break;
case NV_BurstLen32:
-#if !IS_ENABLED(CONFIG_GFXUMA)
+#if !CONFIG(GFXUMA)
val = 0; /* 64 byte mode */
-#elif IS_ENABLED(CONFIG_GFXUMA)
+#elif CONFIG(GFXUMA)
val = 1; /* 32 byte mode */
#endif
break;
@@ -214,9 +214,9 @@
case NV_BottomIO:
case NV_BottomUMA:
/* address bits [31:24] */
-#if !IS_ENABLED(CONFIG_GFXUMA)
+#if !CONFIG(GFXUMA)
val = (CONFIG_MMCONF_BASE_ADDRESS >> 24);
-#elif IS_ENABLED(CONFIG_GFXUMA)
+#elif CONFIG(GFXUMA)
#if (CONFIG_MMCONF_BASE_ADDRESS < (MAXIMUM_GFXUMA_SIZE + MINIMUM_DRAM_BELOW_4G))
#error "MMCONF_BASE_ADDRESS is too small"
#endif
@@ -360,12 +360,12 @@
if (pDCTstat->DimmRegistered[i + 1])
ch2_registered = 1;
}
- if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) {
+ if (CONFIG(DEBUG_RAM_SETUP)) {
printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 1: %d DIMM(s) detected\n", ch1_count);
printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 2: %d DIMM(s) detected\n", ch2_count);
}
-#if IS_ENABLED(CONFIG_DIMM_DDR3)
+#if CONFIG(DIMM_DDR3)
for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) {
if (pDCTstat->DIMMValid & (1 << i))
ch1_voltage |= pDCTstat->DimmConfiguredVoltage[i];
@@ -421,7 +421,7 @@
}
-#if IS_ENABLED(CONFIG_DIMM_DDR2)
+#if CONFIG(DIMM_DDR2)
void mctSaveDQSSigTmg_D(void)
{
}
@@ -470,7 +470,7 @@
{
}
-#if IS_ENABLED(CONFIG_DIMM_DDR3)
+#if CONFIG(DIMM_DDR3)
void vErratum372(struct DCTStatStruc *pDCTstat)
{
msr_t msr = rdmsr(NB_CFG_MSR);
@@ -504,7 +504,7 @@
void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
{
-#if IS_ENABLED(CONFIG_DIMM_DDR3)
+#if CONFIG(DIMM_DDR3)
/* FIXME : as of 25.6.2010 errata 350 and 372 should apply to ((RB|BL|DA)-C[23])|(HY-D[01])|(PH-E0) but I don't find constants for all of them */
if (pDCTstatA->LogicalCPUID & (AMD_DRBH_Cx | AMD_DR_Dx)) {
vErratum372(pDCTstatA);
@@ -513,7 +513,7 @@
#endif
}
-#if IS_ENABLED(CONFIG_DIMM_DDR3)
+#if CONFIG(DIMM_DDR3)
u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val)
{
if (pDCTstatA->LogicalCPUID & AMD_DR_Bx) {
@@ -534,7 +534,7 @@
return mctGetLogicalCPUID(node);
}
-#if IS_ENABLED(CONFIG_DIMM_DDR2)
+#if CONFIG(DIMM_DDR2)
u8 mctSetNodeBoundary_D(void)
{
return 0;
diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c
index c24fb2d..3f86427 100644
--- a/src/northbridge/amd/pi/00630F01/northbridge.c
+++ b/src/northbridge/amd/pi/00630F01/northbridge.c
@@ -36,7 +36,7 @@
#include <assert.h>
#include <northbridge/amd/pi/nb_common.h>
#include <northbridge/amd/agesa/agesa_helper.h>
-#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
+#if CONFIG(BINARYPI_LEGACY_WRAPPER)
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#endif
@@ -370,7 +370,7 @@
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
- if (IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) {
+ if (CONFIG(MULTIPLE_VGA_ADAPTERS)) {
extern struct device *vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
@@ -611,7 +611,7 @@
static void domain_enable_resources(struct device *dev)
{
-#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
+#if CONFIG(BINARYPI_LEGACY_WRAPPER)
/* Must be called after PCI enumeration and resource allocation */
if (!acpi_is_wakeup_s3()) {
/* Enable MMIO on AMD CPU Address Map Controller */
diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c
index 19fb814..bf7c59a 100644
--- a/src/northbridge/amd/pi/00660F01/northbridge.c
+++ b/src/northbridge/amd/pi/00660F01/northbridge.c
@@ -35,7 +35,7 @@
#include <arch/acpigen.h>
#include <northbridge/amd/pi/nb_common.h>
#include <northbridge/amd/agesa/agesa_helper.h>
-#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
+#if CONFIG(BINARYPI_LEGACY_WRAPPER)
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#endif
@@ -355,7 +355,7 @@
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
+#if CONFIG(MULTIPLE_VGA_ADAPTERS)
extern struct device *vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
@@ -610,7 +610,7 @@
static void domain_enable_resources(struct device *dev)
{
-#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
+#if CONFIG(BINARYPI_LEGACY_WRAPPER)
/* Must be called after PCI enumeration and resource allocation */
if (!acpi_is_wakeup_s3())
AGESAWRAPPER(amdinitmid);
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 9bbb2de..eb38c42 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -37,7 +37,7 @@
#include <arch/acpigen.h>
#include <northbridge/amd/pi/nb_common.h>
#include <northbridge/amd/agesa/agesa_helper.h>
-#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
+#if CONFIG(BINARYPI_LEGACY_WRAPPER)
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#endif
@@ -371,7 +371,7 @@
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
+#if CONFIG(MULTIPLE_VGA_ADAPTERS)
extern struct device *vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
@@ -843,7 +843,7 @@
static void domain_enable_resources(struct device *dev)
{
-#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
+#if CONFIG(BINARYPI_LEGACY_WRAPPER)
/* Must be called after PCI enumeration and resource allocation */
if (!acpi_is_wakeup_s3())
AGESAWRAPPER(amdinitmid);
diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c
index b05c120..28f2876 100644
--- a/src/northbridge/amd/pi/agesawrapper.c
+++ b/src/northbridge/amd/pi/agesawrapper.c
@@ -55,8 +55,8 @@
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
- AmdResetParams.FchInterface.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
- if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON))
+ AmdResetParams.FchInterface.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
+ if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON))
AmdResetParams.FchInterface.Xhci1Enable = TRUE;
AmdResetParams.FchInterface.SataEnable = !((CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3));
@@ -96,7 +96,7 @@
* init_timer() needs to be called on CZ PI, because AGESA resets the LAPIC reload value
* on the AMD_INIT_EARLY call
*/
- if (IS_ENABLED(CONFIG_CPU_AMD_PI_00660F01))
+ if (CONFIG(CPU_AMD_PI_00660F01))
init_timer();
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
@@ -299,7 +299,7 @@
const AMD_MODULE_HEADER* module;
size_t file_size;
- if (IS_ENABLED(CONFIG_VBOOT)) {
+ if (CONFIG(VBOOT)) {
/* Use phys. location in flash and prevent vboot from searching cbmem */
agesa = (void *)CONFIG_AGESA_BINARY_PI_LOCATION;
file_size = 0x100000;
diff --git a/src/northbridge/amd/pi/agesawrapper.h b/src/northbridge/amd/pi/agesawrapper.h
index e5971d8..e1cec43 100644
--- a/src/northbridge/amd/pi/agesawrapper.h
+++ b/src/northbridge/amd/pi/agesawrapper.h
@@ -16,7 +16,7 @@
#ifndef _AGESAWRAPPER_H_
#define _AGESAWRAPPER_H_
-#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
+#if CONFIG(BINARYPI_LEGACY_WRAPPER)
#include <stdint.h>
#include <Porting.h>
@@ -51,7 +51,7 @@
#endif
-#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
+#if CONFIG(BINARYPI_LEGACY_WRAPPER)
const void *agesawrapper_locate_module (const CHAR8 name[8]);
VOID OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly);
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index fcf347c..3bb1f67 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -54,7 +54,7 @@
// Unfortunately the code seems to chew up several K of space.
//#define VALIDATE_DIMM_COMPATIBILITY
-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
+#if CONFIG(DEBUG_RAM_SETUP)
#define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x)
#define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
#define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
index 7977575..ec36c06 100644
--- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
+++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
@@ -97,7 +97,7 @@
if (config->MrcRmtCpgcNumBursts) {
UpdData->PcdMrcRmtCpgcNumBursts = config->MrcRmtCpgcNumBursts;
}
-#if IS_ENABLED(CONFIG_ENABLE_FSP_FAST_BOOT)
+#if CONFIG(ENABLE_FSP_FAST_BOOT)
UpdData->PcdFastboot = UPD_ENABLE;
#endif
/*
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 4a5ebbd..648aa48 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -190,7 +190,7 @@
mmio = res2mmio(gtt_res, 0, 0);
- if (!IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {
+ if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
/* PCI Init, will run VBIOS */
printk(BIOS_DEBUG, "Initialising IGD using VBIOS\n");
pci_dev_init(dev);
@@ -205,7 +205,7 @@
/* Post VBIOS init */
gma_pm_init_post_vbios(dev, edid_lvds.ascii_string);
- if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {
+ if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1;
if (vga_disable) {
printk(BIOS_INFO,
diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl
index e9d3520..0f0d383 100644
--- a/src/northbridge/intel/haswell/acpi/haswell.asl
+++ b/src/northbridge/intel/haswell/acpi/haswell.asl
@@ -33,7 +33,7 @@
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
-#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)
+#if CONFIG(CHROMEOS_RAMOOPS)
Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
#endif
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 3b043a3..0fd0228 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -35,7 +35,7 @@
#include "chip.h"
#include "haswell.h"
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
#endif
@@ -240,7 +240,7 @@
* after we power up the AUX channel until we can talk to it.
* So get that going right now. We can't turn on the panel, yet, just VDD.
*/
- if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
+ if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
gtt_write(PCH_PP_CONTROL, PCH_PP_UNLOCK| EDP_FORCE_VDD | PANEL_POWER_RESET);
}
}
@@ -475,7 +475,7 @@
int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1;
- if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {
+ if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
if (vga_disable) {
printk(BIOS_INFO,
"IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n");
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index ac0b84f..ad4563b 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -395,7 +395,7 @@
mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource(dev, index++, (0xc0000 >> 10),
(0x100000 - 0xc0000) >> 10);
-#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)
+#if CONFIG(CHROMEOS_RAMOOPS)
reserved_ram_resource(dev, index++,
CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index bf88418..91959c7 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -31,7 +31,7 @@
*/
/* Debugging macros. */
-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
+#if CONFIG(DEBUG_RAM_SETUP)
#define PRINT_DEBUG(x...) printk(BIOS_DEBUG, x)
#define DUMPNORTH() dump_pci_device(NB)
#else
@@ -297,7 +297,7 @@
* 0 = 3 clocks of RAS# precharge
* 1 = 2 clocks of RAS# precharge
*/
-#if IS_ENABLED(CONFIG_SDRAMPWR_4DIMM)
+#if CONFIG(SDRAMPWR_4DIMM)
SDRAMC + 0, 0x00, 0x10, /* The board has 4 DIMM slots. */
#else
SDRAMC + 0, 0x00, 0x00, /* The board has 3 DIMM slots. */
@@ -460,7 +460,7 @@
}
}
- if (IS_ENABLED(CONFIG_SDRAMPWR_4DIMM)) {
+ if (CONFIG(SDRAMPWR_4DIMM)) {
/*
* For a 4 DIMM board, based on ASUS P2B-LS mainboard.
*
diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h
index e20d559..4711359 100644
--- a/src/northbridge/intel/i440bx/raminit.h
+++ b/src/northbridge/intel/i440bx/raminit.h
@@ -29,7 +29,7 @@
void sdram_initialize(void);
/* Debug */
-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
+#if CONFIG(DEBUG_RAM_SETUP)
void dump_spd_registers(void);
void dump_pci_device(unsigned dev);
#else
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 1913b52..7ab2525 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -93,7 +93,7 @@
}
printk(BIOS_DEBUG, "\n");
- if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC))
+ if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC))
printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
}
@@ -143,7 +143,7 @@
}
printk(BIOS_DEBUG, "\n");
- if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
+ if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
}
@@ -237,7 +237,7 @@
/* Egress Port Virtual Channel 1 Configuration */
reg32 = EPBAR32(0x2c);
reg32 &= 0xffffff00;
- if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
+ if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
if ((MCHBAR32(CLKCFG) & 7) == 0)
reg32 |= 0x1a; /* 1067MHz */
}
@@ -256,7 +256,7 @@
reg32 |= (0x0a << 16);
EPBAR32(EPVC1RCAP) = reg32;
- if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
+ if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
if ((MCHBAR32(CLKCFG) & 7) == 0) { /* 1067MHz */
EPBAR32(EPVC1IST + 0) = 0x01380138;
EPBAR32(EPVC1IST + 4) = 0x01380138;
@@ -941,14 +941,14 @@
i945_setup_dmi_rcrb();
- if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
+ if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
i945_setup_pci_express_x16();
i945_setup_root_complex_topology();
-#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if !CONFIG(HAVE_ACPI_RESUME)
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
+#if CONFIG(DEBUG_RAM_SETUP)
sdram_dump_mchbar_registers();
{
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 26b6c84..633b09d 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -236,9 +236,9 @@
BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) /
(pixel_n + 2) / (pixel_p1 * pixel_p2));
- printk(BIOS_INFO, "VGA mode: %s\n", IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER) ?
+ printk(BIOS_INFO, "VGA mode: %s\n", CONFIG(LINEAR_FRAMEBUFFER) ?
"Linear framebuffer" : "text");
- if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
+ if (CONFIG(LINEAR_FRAMEBUFFER)) {
/* Disable panel fitter (we're in native resolution). */
write32(mmiobase + PF_CTL(0), 0);
write32(mmiobase + PF_WIN_SZ(0), 0);
@@ -301,7 +301,7 @@
((vactive + bottom_border + vfront_porch + vsync - 1) << 16)
| (vactive + bottom_border + vfront_porch - 1));
- if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
+ if (CONFIG(LINEAR_FRAMEBUFFER)) {
write32(mmiobase + PIPESRC(1), ((hactive - 1) << 16)
| (vactive - 1));
} else {
@@ -380,7 +380,7 @@
else
printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n");
- if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
+ if (CONFIG(LINEAR_FRAMEBUFFER)) {
printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n",
(void *)pgfx, hactive * vactive * 4);
memset((void *)pgfx, 0x00, hactive * vactive * 4);
@@ -660,7 +660,7 @@
int err;
- if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
+ if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
panel_setup(mmiobase, dev);
/* probe if VGA is connected and always run */
@@ -704,7 +704,7 @@
int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1;
- if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
+ if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
if (acpi_is_wakeup_s3()) {
printk(BIOS_INFO,
"Skipping native VGA initialization when resuming from ACPI S3.\n");
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index a9bfde7..a93cf1e 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -33,7 +33,7 @@
#include <timestamp.h>
/* Debugging macros. */
-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
+#if CONFIG(DEBUG_RAM_SETUP)
#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x)
#else
#define PRINTK_DEBUG(x...)
@@ -96,7 +96,7 @@
read32((void *)offset);
}
-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
+#if CONFIG(DEBUG_RAM_SETUP)
void sdram_dump_mchbar_registers(void)
{
int i;
@@ -112,7 +112,7 @@
static int memclk(void)
{
- int offset = IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0;
+ int offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0;
switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
case 1: return 400;
@@ -127,7 +127,7 @@
static u16 fsbclk(void)
{
- if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) {
+ if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) {
switch (MCHBAR32(CLKCFG) & 7) {
case 0: return 400;
case 1: return 533;
@@ -137,7 +137,7 @@
MCHBAR32(CLKCFG) & 7);
}
return 0xffff;
- } else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
+ } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
switch (MCHBAR32(CLKCFG) & 7) {
case 0: return 1066;
case 1: return 533;
@@ -386,7 +386,7 @@
bytes_read = i2c_eeprom_read(device, 0, 64, raw_spd);
printk(BIOS_DEBUG, "Reading SPD using i2c block operation.\n");
- if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) && bytes_read > 0)
+ if (CONFIG(DEBUG_RAM_SETUP) && bytes_read > 0)
hexdump(raw_spd, bytes_read);
if (bytes_read != 64) {
/* Try again with SMBUS byte read */
@@ -394,7 +394,7 @@
" trying smbus byte operation.\n");
for (j = 0; j < 64; j++)
raw_spd[j] = spd_read_byte(device, j);
- if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP))
+ if (CONFIG(DEBUG_RAM_SETUP))
hexdump(raw_spd, 64);
}
@@ -404,7 +404,7 @@
continue;
}
- if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP))
+ if (CONFIG(DEBUG_RAM_SETUP))
dram_print_spd_ddr2(&dimm_info);
if (dimm_info.flags.is_ecc)
@@ -841,7 +841,7 @@
return nc;
}
-#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)
+#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)
/* Strength multiplier tables */
static const u8 dual_channel_strength_multiplier[] = {
0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
@@ -896,7 +896,7 @@
0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
};
-#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)
+#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)
static const u8 dual_channel_strength_multiplier[] = {
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
@@ -1027,7 +1027,7 @@
MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
/* We drive both channels with the same speed */
- if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) {
+ if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) {
switch (sysinfo->memory_frequency) {
case 400:
channeldll = 0x26262626; break;
@@ -1036,7 +1036,7 @@
case 667:
channeldll = 0x11111111; break;
}
- } else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
+ } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
switch (sysinfo->memory_frequency) {
case 400:
channeldll = 0x33333333; break;
@@ -1052,7 +1052,7 @@
MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = channeldll;
MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = channeldll;
MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = channeldll;
- if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
+ if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff;
MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff;
}
@@ -1769,7 +1769,7 @@
{
u32 clkcfg;
u8 reg8;
- u8 offset = IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0;
+ u8 offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0;
printk(BIOS_DEBUG, "Setting Memory Frequency... ");
@@ -1854,7 +1854,7 @@
/**
* We add the indices according to our clocks from CLKCFG.
*/
-#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)
+#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)
static const u32 data_clock_crossing[] = {
0x00100401, 0x00000000, /* DDR400 FSB400 */
0xffffffff, 0xffffffff, /* nonexistent */
@@ -1899,7 +1899,7 @@
0xffffffff, 0xffffffff, /* nonexistent */
};
-#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)
+#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)
/* i945 G/P */
static const u32 data_clock_crossing[] = {
0xffffffff, 0xffffffff, /* nonexistent */
@@ -2119,7 +2119,7 @@
if (sysinfo->interleaved) {
reg32 = MCHBAR32(DCC);
-#if IS_ENABLED(CONFIG_CHANNEL_XOR_RANDOMIZATION)
+#if CONFIG(CHANNEL_XOR_RANDOMIZATION)
reg32 &= ~(1 << 10);
reg32 |= (1 << 9);
#else
@@ -2175,7 +2175,7 @@
reg32 |= (1 << 12) | (1 << 11);
MCHBAR32(C1DRC1) = reg32;
- if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) {
+ if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) {
if (i945_silicon_revision() > 1) {
/* FIXME bits 5 and 0 only if PCIe graphics is disabled */
u16 peg_bits = (1 << 5) | (1 << 0);
@@ -2493,9 +2493,9 @@
{
u8 clocks[2] = { 0, 0 };
-#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)
+#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)
#define CLOCKS_WIDTH 2
-#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)
+#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)
#define CLOCKS_WIDTH 3
#endif
if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
@@ -2510,7 +2510,7 @@
if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
-#if IS_ENABLED(CONFIG_OVERRIDE_CLOCK_DISABLE)
+#if CONFIG(OVERRIDE_CLOCK_DISABLE)
/* Usually system firmware turns off system memory clock signals
* to unused SO-DIMM slots to reduce EMI and power consumption.
* However, the Kontron 986LCD-M does not like unused clock
@@ -2755,7 +2755,7 @@
* Program Graphics Frequency
* Set core display and render clock on 945GC to the max
*/
- if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
+ if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
sdram_program_graphics_frequency(&sysinfo);
else
pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534);
diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h
index 98bdc02..2d1eee6 100644
--- a/src/northbridge/intel/i945/raminit.h
+++ b/src/northbridge/intel/i945/raminit.h
@@ -70,7 +70,7 @@
int fixup_i945_errata(void);
void udelay(u32 us);
-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
+#if CONFIG(DEBUG_RAM_SETUP)
void sdram_dump_mchbar_registers(void);
#endif
#endif /* RAMINIT_H */
diff --git a/src/northbridge/intel/nehalem/acpi/nehalem.asl b/src/northbridge/intel/nehalem/acpi/nehalem.asl
index 664022b..df8aad7 100644
--- a/src/northbridge/intel/nehalem/acpi/nehalem.asl
+++ b/src/northbridge/intel/nehalem/acpi/nehalem.asl
@@ -33,7 +33,7 @@
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
-#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)
+#if CONFIG(CHROMEOS_RAMOOPS)
Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
#endif
diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c
index 2c958a4..a5cac7b 100644
--- a/src/northbridge/intel/nehalem/early_init.c
+++ b/src/northbridge/intel/nehalem/early_init.c
@@ -73,7 +73,7 @@
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33);
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33);
-#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
+#if CONFIG(ELOG_BOOT_COUNT)
/* Increment Boot Counter for non-S3 resume */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3)
@@ -82,7 +82,7 @@
printk(BIOS_DEBUG, " done.\n");
-#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
+#if CONFIG(ELOG_BOOT_COUNT)
/* Increment Boot Counter except when resuming from S3 */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index be17e2f..86fc583 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -603,7 +603,7 @@
/* Init graphics power management */
gma_pm_init_pre_vbios(dev);
- if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {
+ if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
struct northbridge_intel_nehalem_config *conf = dev->chip_info;
int lightup_ok;
printk(BIOS_SPEW, "Initializing VGA without OPROM.");
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
index 6906714..8a4f64c 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -78,7 +78,7 @@
reserved_ram_resource(dev, index++, 0xc0000 >> 10,
(0x100000 - 0xc0000) >> 10);
-#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)
+#if CONFIG(CHROMEOS_RAMOOPS)
reserved_ram_resource(dev, index++,
CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
@@ -90,7 +90,7 @@
assign_resources(dev->link_list);
}
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
static const char *northbridge_acpi_name(const struct device *dev)
{
if (dev->path.type == DEVICE_PATH_DOMAIN)
@@ -114,7 +114,7 @@
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
.acpi_name = northbridge_acpi_name,
#endif
};
diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c
index 73a8240..8bacc77 100644
--- a/src/northbridge/intel/pineview/gma.c
+++ b/src/northbridge/intel/pineview/gma.c
@@ -268,7 +268,7 @@
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
- if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
+ if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
/* PCI Init, will run VBIOS */
pci_dev_init(dev);
} else {
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index 4cdb27a..5aea59e 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -28,7 +28,7 @@
#include <string.h>
/* Debugging macros. */
-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
+#if CONFIG(DEBUG_RAM_SETUP)
#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x)
#else
#define PRINTK_DEBUG(x...)
@@ -134,7 +134,7 @@
d->tRCD = d->spd_data[29];
d->tWR = d->spd_data[36];
d->ranks = d->sides; // XXX
-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
+#if CONFIG(DEBUG_RAM_SETUP)
const char *ubso[2] = { "UB", "SO" };
#endif
PRINTK_DEBUG("%s-DIMM %d\n", &ubso[d->type][0], i);
@@ -311,7 +311,7 @@
}
}
-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
+#if CONFIG(DEBUG_RAM_SETUP)
static u32 fsb_reg_to_mhz(u32 speed)
{
return (speed * 133) + 667;
diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
index 7369203..dce9f67 100644
--- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
@@ -35,7 +35,7 @@
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
-#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)
+#if CONFIG(CHROMEOS_RAMOOPS)
Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
#endif
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 44eebf3..ad579c6 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -59,7 +59,7 @@
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33);
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
-#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
+#if CONFIG(ELOG_BOOT_COUNT)
/* Increment Boot Counter for non-S3 resume */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3)
@@ -68,7 +68,7 @@
printk(BIOS_DEBUG, " done.\n");
-#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
+#if CONFIG(ELOG_BOOT_COUNT)
/* Increment Boot Counter except when resuming from S3 */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)
@@ -159,7 +159,7 @@
* As the MRC has its own initialization code skip it. */
if (((pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID) &
BASE_REV_MASK) != BASE_REV_IVB) ||
- IS_ENABLED(CONFIG_HAVE_MRC))
+ CONFIG(HAVE_MRC))
return;
deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index ce2abd9..00180fe 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -625,7 +625,7 @@
/* Init graphics power management */
gma_pm_init_pre_vbios(dev);
- if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
+ if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT))
/* PCI Init, will run VBIOS */
pci_dev_init(dev);
@@ -636,7 +636,7 @@
/* Running graphics init on S3 breaks Linux drm driver. */
if (!acpi_is_wakeup_s3() &&
- IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {
+ CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
if (vga_disable) {
printk(BIOS_INFO,
"IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n");
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index ab0554c..e58a0eb 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -98,7 +98,7 @@
reserved_ram_resource(dev, index++, 0xc0000 >> 10,
(0x100000 - 0xc0000) >> 10);
-#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)
+#if CONFIG(CHROMEOS_RAMOOPS)
reserved_ram_resource(dev, index++,
CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c
index 53fb4d3..16bc314 100644
--- a/src/northbridge/intel/sandybridge/pcie.c
+++ b/src/northbridge/intel/sandybridge/pcie.c
@@ -28,7 +28,7 @@
dev->enabled = 0;
}
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
static const char *pcie_acpi_name(const struct device *dev)
{
assert(dev);
@@ -90,7 +90,7 @@
.disable = pcie_disable,
.init = pci_dev_init,
.ops_pci = &pci_ops,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
.acpi_name = pcie_acpi_name,
#endif
};
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index caba76e..3f62d10 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -210,7 +210,7 @@
printram("XMP profile supports %u DIMMs, but %u DIMMs are installed.\n",
dimm->dimm[channel][slot].dimms_per_channel,
dimms_on_channel);
- if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS))
+ if (CONFIG(NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS))
printk(BIOS_WARNING, "XMP maximum DIMMs will be ignored.\n");
else
spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]);
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 6bda9ed..fda662f 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -390,7 +390,7 @@
/* If this is zero, it just means devicetree.cb didn't set it */
if (!cfg || cfg->max_mem_clock_mhz == 0) {
- if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES))
+ if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES))
return TCK_1333MHZ;
rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 853fdb8..852da7a 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -41,7 +41,7 @@
* MRC scrambler seed offsets should be reserved in
* mainboard cmos.layout and not covered by checksum.
*/
-#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
+#if CONFIG(USE_OPTION_TABLE)
#include "option_table.h"
#define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3)
#define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3)
@@ -241,7 +241,7 @@
}
/* mrc.bin reconfigures USB, so reinit it to have debug */
- if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM))
+ if (CONFIG(USBDEBUG_IN_PRE_RAM))
usbdebug_hw_init(true);
/* For reference print the System Agent version
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index 9cb3df3..5ccc77e 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -18,7 +18,7 @@
#include <arch/io.h>
#include <device/pci_ops.h>
#include "iomap.h"
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)
+#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
#include <southbridge/intel/i82801gx/i82801gx.h> /* DEFAULT_PMBASE */
#else
#include <southbridge/intel/i82801jx/i82801jx.h> /* DEFAULT_PMBASE */
diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c
index 7e91cc5..8de568a 100644
--- a/src/northbridge/intel/x4x/gma.c
+++ b/src/northbridge/intel/x4x/gma.c
@@ -36,9 +36,9 @@
#include <pc80/vga.h>
#include <pc80/vga_io.h>
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801JX)
+#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX)
#include <southbridge/intel/i82801jx/nvs.h>
-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)
+#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
#include <southbridge/intel/i82801gx/nvs.h>
#endif
@@ -71,7 +71,7 @@
int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1;
- if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {
+ if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
if (vga_disable) {
printk(BIOS_INFO,
"IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n");
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index ea00f29..72ef1a9 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -25,7 +25,7 @@
#include <halt.h>
#include <lib.h>
#include "iomap.h"
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)
+#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
#include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */
#else
#include <southbridge/intel/i82801jx/i82801jx.h> /* smbus_read_byte */
@@ -174,7 +174,7 @@
return CB_ERR;
}
- if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP))
+ if (CONFIG(DEBUG_RAM_SETUP))
dram_print_spd_ddr2(&decoded_dimm);
if (!(decoded_dimm.width & (0x08 | 0x10))) {
@@ -383,7 +383,7 @@
if (spd_decode_ddr3(&decoded_dimm, raw_spd) != SPD_STATUS_OK)
return CB_ERR;
- if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP))
+ if (CONFIG(DEBUG_RAM_SETUP))
dram_print_spd_ddr3(&decoded_dimm);
/* x4 DIMMs are not supported (true for both ddr2 and ddr3) */
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index d14809e..f172623 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -21,7 +21,7 @@
#include <console/console.h>
#include <commonlib/helpers.h>
#include <delay.h>
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)
+#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
#include <southbridge/intel/i82801gx/i82801gx.h>
#else
#include <southbridge/intel/i82801jx/i82801jx.h>
diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c
index 209601d..41ea154 100644
--- a/src/northbridge/via/vx900/lpc.c
+++ b/src/northbridge/via/vx900/lpc.c
@@ -244,7 +244,7 @@
.device = PCI_DEVICE_ID_VIA_VX900_LPC,
};
-#if IS_ENABLED(CONFIG_PIRQ_ROUTE)
+#if CONFIG(PIRQ_ROUTE)
void pirq_assign_irqs(const u8 *pirq)
{
struct device *lpc;