coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S
index cdc8e93..3f2a7ae 100644
--- a/src/drivers/intel/fsp1_1/after_raminit.S
+++ b/src/drivers/intel/fsp1_1/after_raminit.S
@@ -30,7 +30,7 @@
/* Switch to the stack in RAM */
movl %eax, %esp
-#if IS_ENABLED(CONFIG_SKIP_FSP_CAR)
+#if CONFIG(SKIP_FSP_CAR)
/* chipset_teardown_car() is expected to disable cache-as-ram. */
call chipset_teardown_car
@@ -87,7 +87,7 @@
* +0: Number of variable MTRRs to clear
*/
-#if IS_ENABLED(CONFIG_SOC_SETS_MSRS)
+#if CONFIG(SOC_SETS_MSRS)
push %esp
call soc_set_mtrrs
@@ -147,7 +147,7 @@
post_code(0x3a)
-#if IS_ENABLED(CONFIG_SOC_SETS_MSRS)
+#if CONFIG(SOC_SETS_MSRS)
call soc_enable_mtrrs
#else
/* Enable MTRR. */
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc
index 70e1ad7..48fcb8f 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc
@@ -189,7 +189,7 @@
.Lhlt:
xchg %al, %ah
-#if IS_ENABLED(CONFIG_POST_IO)
+#if CONFIG(POST_IO)
outb %al, $CONFIG_POST_IO_PORT
#else
post_code(POST_DEAD_CODE)
diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c
index 2c5e9a7..2702b5a 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.c
+++ b/src/drivers/intel/fsp1_1/fsp_util.c
@@ -102,7 +102,7 @@
(u8)((fsp_header->ImageRevision >> 16) & 0xff),
(u8)((fsp_header->ImageRevision >> 8) & 0xff),
(u8)(fsp_header->ImageRevision & 0xff));
-#if IS_ENABLED(CONFIG_DISPLAY_FSP_ENTRY_POINTS)
+#if CONFIG(DISPLAY_FSP_ENTRY_POINTS)
printk(BIOS_SPEW, "FSP Entry Points:\n");
printk(BIOS_SPEW, " 0x%p: Image Base\n", fsp_base);
printk(BIOS_SPEW, " 0x%p: TempRamInit\n",
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 7fed2a1..2dd5c77 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -51,7 +51,7 @@
VPD_DATA_REGION *vpd_ptr;
UPD_DATA_REGION *upd_ptr;
int fsp_verification_failure = 0;
-#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
+#if CONFIG(DISPLAY_HOBS)
unsigned long int data;
EFI_PEI_HOB_POINTERS hob_ptr;
#endif
@@ -101,13 +101,13 @@
soc_memory_init_params(params, &memory_init_params);
mainboard_memory_init_params(params, &memory_init_params);
- if (IS_ENABLED(CONFIG_MMA))
+ if (CONFIG(MMA))
setup_mma(&memory_init_params);
post_code(POST_MEM_PREINIT_PREP_END);
/* Display the UPD data */
- if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
+ if (CONFIG(DISPLAY_UPD_DATA))
soc_display_memory_init_params(original_params,
&memory_init_params);
@@ -146,7 +146,7 @@
}
/* Display SMM area */
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if CONFIG(HAVE_SMI_HANDLER)
char *smm_base;
size_t smm_size;
@@ -162,7 +162,7 @@
fsp_reserved_bytes);
} else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
fsp_reserved_bytes)) {
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if CONFIG(HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
/* Failed S3 resume, reset to come up cleanly */
/* FIXME: A "system" reset is likely enough: */
@@ -194,7 +194,7 @@
memory_info_hob);
}
-#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
+#if CONFIG(DISPLAY_HOBS)
if (hob_list_ptr == NULL)
die("ERROR - HOB pointer is NULL!\n");
@@ -266,7 +266,7 @@
(unsigned int)fsp_reserved_memory_area))) {
fsp_verification_failure = 1;
printk(BIOS_DEBUG, "ERROR - Reserving FSP memory area!\n");
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if CONFIG(HAVE_SMI_HANDLER)
if (cbmem_root != NULL) {
size_t delta_bytes = (unsigned int)smm_base
- cbmem_root->PhysicalStart
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
index 864ab45..814bddf 100644
--- a/src/drivers/intel/fsp1_1/ramstage.c
+++ b/src/drivers/intel/fsp1_1/ramstage.c
@@ -55,7 +55,7 @@
int missing_hob = 0;
void *hob_list_ptr = get_hob_list();
- if (!IS_ENABLED(CONFIG_DISPLAY_HOBS))
+ if (!CONFIG(DISPLAY_HOBS))
return;
/* Verify the HOBs */
@@ -117,12 +117,12 @@
soc_silicon_init_params(&silicon_init_params);
/* Locate VBT and pass to FSP GOP */
- if (IS_ENABLED(CONFIG_RUN_FSP_GOP))
+ if (CONFIG(RUN_FSP_GOP))
load_vbt(is_s3_wakeup, &silicon_init_params);
mainboard_silicon_init_params(&silicon_init_params);
/* Display the UPD data */
- if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
+ if (CONFIG(DISPLAY_UPD_DATA))
soc_display_silicon_init_params(original_params,
&silicon_init_params);
@@ -139,7 +139,7 @@
printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
/* Mark graphics init done after SiliconInit if VBT was provided */
-#if IS_ENABLED(CONFIG_RUN_FSP_GOP)
+#if CONFIG(RUN_FSP_GOP)
/* GraphicsConfigPtr doesn't exist in Quark X1000's FSP, so this needs
* to be #if'd out instead of using if (). */
if (silicon_init_params.GraphicsConfigPtr)
@@ -152,10 +152,10 @@
static void fsp_cache_save(struct prog *fsp)
{
- if (IS_ENABLED(CONFIG_DISPLAY_SMM_MEMORY_MAP))
+ if (CONFIG(DISPLAY_SMM_MEMORY_MAP))
smm_memory_map();
- if (IS_ENABLED(CONFIG_NO_STAGE_CACHE))
+ if (CONFIG(NO_STAGE_CACHE))
return;
printk(BIOS_DEBUG, "FSP: Saving binary in cache\n");
@@ -192,7 +192,7 @@
if (load_done)
return;
- if (is_s3_wakeup && !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) {
+ if (is_s3_wakeup && !CONFIG(NO_STAGE_CACHE)) {
printk(BIOS_DEBUG, "FSP: Loading binary from cache\n");
stage_cache_load_stage(STAGE_REFCODE, &fsp);
} else {
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 31d696f..ebb6a66 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -52,13 +52,13 @@
timestamp_add_now(TS_START_ROMSTAGE);
/* Load microcode before RAM init */
- if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
+ if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS))
intel_update_microcode_from_cbfs();
memset(&pei_data, 0, sizeof(pei_data));
/* Display parameters */
- if (!IS_ENABLED(CONFIG_NO_MMCONF_SUPPORT))
+ if (!CONFIG(NO_MMCONF_SUPPORT))
printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
CONFIG_MMCONF_BASE_ADDRESS);
printk(BIOS_INFO, "Using FSP 1.1\n");
@@ -104,7 +104,7 @@
pei_data->boot_mode = params->power_state->prev_sleep_state;
s3wake = params->power_state->prev_sleep_state == ACPI_S3;
- if (IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) && !s3wake)
+ if (CONFIG(ELOG_BOOT_COUNT) && !s3wake)
boot_count_increment();
/* Perform remaining SOC initialization */
@@ -119,7 +119,7 @@
/* Recovery mode does not use MRC cache */
printk(BIOS_DEBUG,
"Recovery mode: not using MRC cache.\n");
- } else if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)
+ } else if (CONFIG(CACHE_MRC_SETTINGS)
&& (!mrc_cache_get_current(MRC_TRAINING_DATA,
params->fsp_version,
&rdev))) {
@@ -128,7 +128,7 @@
region_device_sz(&rdev);
params->pei_data->saved_data = rdev_mmap_full(&rdev);
/* Assume boot device is memory mapped. */
- assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED));
+ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
} else if (params->pei_data->boot_mode == ACPI_S3) {
/* Waking from S3 and no cache. */
printk(BIOS_DEBUG,
@@ -146,7 +146,7 @@
timestamp_add_now(TS_AFTER_INITRAM);
/* Save MRC output */
- if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) {
+ if (CONFIG(CACHE_MRC_SETTINGS)) {
printk(BIOS_DEBUG, "MRC data at %p %d bytes\n",
pei_data->data_to_save, pei_data->data_to_save_size);
if ((params->pei_data->boot_mode != ACPI_S3)
@@ -214,7 +214,7 @@
memory_info_hob = (FSP_SMBIOS_MEMORY_INFO *)(hob_ptr + 1);
/* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */
- if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) {
+ if (CONFIG(DISPLAY_HOBS)) {
printk(BIOS_DEBUG, "FSP_SMBIOS_MEMORY_INFO HOB\n");
printk(BIOS_DEBUG, " 0x%02x: Revision\n",
memory_info_hob->Revision);
diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c
index eb2a637..88ff36a 100644
--- a/src/drivers/intel/fsp1_1/stack.c
+++ b/src/drivers/intel/fsp1_1/stack.c
@@ -116,7 +116,7 @@
slot = stack_push32(slot, aligned_ram | MTRR_TYPE_WRBACK);
num_mtrrs++;
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if CONFIG(HAVE_SMI_HANDLER)
void *smm_base;
size_t smm_size;
uint32_t tseg_base;
diff --git a/src/drivers/intel/fsp1_1/vbt.c b/src/drivers/intel/fsp1_1/vbt.c
index 90012ff..51d0f59 100644
--- a/src/drivers/intel/fsp1_1/vbt.c
+++ b/src/drivers/intel/fsp1_1/vbt.c
@@ -34,7 +34,7 @@
/* Get VBT data */
vbt_data = locate_vbt(&vbt_len);
if (vbt_data != NULL) {
- if (IS_ENABLED(CONFIG_DISPLAY_VBT)) {
+ if (CONFIG(DISPLAY_VBT)) {
/* Display the vbt file contents */
printk(BIOS_DEBUG, "VBT Data:\n");
hexdump(vbt_data, vbt_len);