coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
index 80023c4..14f5f7a 100644
--- a/src/arch/arm/armv7/mmu.c
+++ b/src/arch/arm/armv7/mmu.c
@@ -37,7 +37,7 @@
#include <arch/cache.h>
-#if IS_ENABLED(CONFIG_ARM_LPAE)
+#if CONFIG(ARM_LPAE)
/* See B3.6.2 of ARMv7 Architecture Reference Manual */
/* TODO: Utilize the contiguous hint flag */
#define ATTR_BLOCK (\
@@ -170,7 +170,7 @@
/* Initialize the new subtable with entries of the same attributes
* (XN bit moves from 4 to 0, set PAGE unless block was unmapped). */
pte_t attr = *pgd_entry & ~(BLOCK_MASK);
- if (!IS_ENABLED(CONFIG_ARM_LPAE) && (attr & (1 << 4)))
+ if (!CONFIG(ARM_LPAE) && (attr & (1 << 4)))
attr = ((attr & ~(1 << 4)) | (1 << 0));
if (attr & ATTR_BLOCK)
attr = (attr & ~ATTR_BLOCK) | ATTR_PAGE;
@@ -208,7 +208,7 @@
/* Always _one_ _damn_ bit that won't fit... (XN moves from 4 to 0) */
pte_t attr = attrs[policy].value;
- if (!IS_ENABLED(CONFIG_ARM_LPAE) && (attr & (1 << 4)))
+ if (!CONFIG(ARM_LPAE) && (attr & (1 << 4)))
attr = ((attr & ~(1 << 4)) | (1 << 0));
/* Mask away high address bits that are handled by upper level table. */
diff --git a/src/arch/arm/include/arch/memlayout.h b/src/arch/arm/include/arch/memlayout.h
index f7837b6..4ba2bf8 100644
--- a/src/arch/arm/include/arch/memlayout.h
+++ b/src/arch/arm/include/arch/memlayout.h
@@ -18,16 +18,16 @@
#ifndef __ARCH_MEMLAYOUT_H
#define __ARCH_MEMLAYOUT_H
-#define SUPERPAGE_SIZE ((1 + IS_ENABLED(CONFIG_ARM_LPAE)) * 1M)
+#define SUPERPAGE_SIZE ((1 + CONFIG(ARM_LPAE)) * 1M)
#define TTB(addr, size) \
REGION(ttb, addr, size, 16K) \
- _ = ASSERT(size >= 16K + IS_ENABLED(CONFIG_ARM_LPAE) * 32, \
+ _ = ASSERT(size >= 16K + CONFIG(ARM_LPAE) * 32, \
"TTB must be 16K (+ 32 for LPAE)!");
#define TTB_SUBTABLES(addr, size) \
- REGION(ttb_subtables, addr, size, IS_ENABLED(CONFIG_ARM_LPAE)*3K + 1K) \
- _ = ASSERT(size % (1K + 3K * IS_ENABLED(CONFIG_ARM_LPAE)) == 0, \
+ REGION(ttb_subtables, addr, size, CONFIG(ARM_LPAE)*3K + 1K) \
+ _ = ASSERT(size % (1K + 3K * CONFIG(ARM_LPAE)) == 0, \
"TTB subtable region must be evenly divisible by table size!");
/* ARM stacks need 8-byte alignment and stay in one place through ramstage. */
diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h
index 9a80217..b2b6a33 100644
--- a/src/arch/arm/include/armv7/arch/cache.h
+++ b/src/arch/arm/include/armv7/arch/cache.h
@@ -134,7 +134,7 @@
/* write translation table base register 0 (TTBR0) */
static inline void write_ttbr0(uint32_t val)
{
- if (IS_ENABLED(CONFIG_ARM_LPAE))
+ if (CONFIG(ARM_LPAE))
asm volatile ("mcrr p15, 0, %[val], %[zero], c2" : :
[val] "r" (val), [zero] "r" (0));
else
diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c
index 7f8e2a0..682715f 100644
--- a/src/arch/arm/tables.c
+++ b/src/arch/arm/tables.c
@@ -32,7 +32,7 @@
bootmem_add_range((uintptr_t)_ttb_subtables, REGION_SIZE(ttb_subtables),
BM_MEM_RAMSTAGE);
- if (!IS_ENABLED(CONFIG_COMMON_CBFS_SPI_WRAPPER))
+ if (!CONFIG(COMMON_CBFS_SPI_WRAPPER))
return;
bootmem_add_range((uintptr_t)_postram_cbfs_cache,
REGION_SIZE(postram_cbfs_cache), BM_MEM_RAMSTAGE);
diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c
index 3f1aa2a..7cf173b 100644
--- a/src/arch/arm64/arm_tf.c
+++ b/src/arch/arm64/arm_tf.c
@@ -56,7 +56,7 @@
SET_PARAM_HEAD(&bl31_params, PARAM_BL31, VERSION_1, 0);
- if (IS_ENABLED(CONFIG_ARM64_USE_SECURE_OS)) {
+ if (CONFIG(ARM64_USE_SECURE_OS)) {
struct prog bl32 = PROG_INIT(PROG_BL32,
CONFIG_CBFS_PREFIX"/secure_os");
diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c
index e32c79a..58a3523 100644
--- a/src/arch/arm64/armv8/exception.c
+++ b/src/arch/arm64/armv8/exception.c
@@ -220,7 +220,7 @@
printk(BIOS_DEBUG, "ARM64: Exception handlers installed.\n");
/* Only spend time testing on debug builds that are trying to detect more errors. */
- if (IS_ENABLED(CONFIG_FATAL_ASSERTS)) {
+ if (CONFIG(FATAL_ASSERTS)) {
printk(BIOS_DEBUG, "ARM64: Testing exception\n");
test_exception();
printk(BIOS_DEBUG, "ARM64: Done test exception\n");
diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c
index c2119f3..fefc0d3 100644
--- a/src/arch/arm64/boot.c
+++ b/src/arch/arm64/boot.c
@@ -30,7 +30,7 @@
arg = prog_entry_arg(prog);
u64 payload_spsr = get_eret_el(EL2, SPSR_USE_L);
- if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE))
+ if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE))
arm_tf_run_bl31((u64)doit, (u64)arg, payload_spsr);
else
transition_to_el2(doit, arg, payload_spsr);
diff --git a/src/arch/arm64/include/armv8/arch/barrier.h b/src/arch/arm64/include/armv8/arch/barrier.h
index 397ac2a..3c3feb6 100644
--- a/src/arch/arm64/include/armv8/arch/barrier.h
+++ b/src/arch/arm64/include/armv8/arch/barrier.h
@@ -30,7 +30,7 @@
#define rmb() asm volatile("dsb ld" : : : "memory")
#define wmb() asm volatile("dsb st" : : : "memory")
-#if IS_ENABLED(CONFIG_SMP)
+#if CONFIG(SMP)
#define barrier() __asm__ __volatile__("": : :"memory")
#endif
diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c
index b0010c4..492eadd 100644
--- a/src/arch/arm64/tables.c
+++ b/src/arch/arm64/tables.c
@@ -30,12 +30,12 @@
{
bootmem_add_range((uintptr_t)_ttb, REGION_SIZE(ttb), BM_MEM_RAMSTAGE);
- if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) &&
+ if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE) &&
REGION_SIZE(bl31) > 0)
bootmem_add_range((uintptr_t)_bl31, REGION_SIZE(bl31),
BM_MEM_BL31);
- if (!IS_ENABLED(CONFIG_COMMON_CBFS_SPI_WRAPPER))
+ if (!CONFIG(COMMON_CBFS_SPI_WRAPPER))
return;
bootmem_add_range((uintptr_t)_postram_cbfs_cache,
REGION_SIZE(postram_cbfs_cache), BM_MEM_RAMSTAGE);
diff --git a/src/arch/mips/bootblock_simple.c b/src/arch/mips/bootblock_simple.c
index 46c961e..40987d8 100644
--- a/src/arch/mips/bootblock_simple.c
+++ b/src/arch/mips/bootblock_simple.c
@@ -26,7 +26,7 @@
/* Mainboard basic init */
bootblock_mainboard_init();
-#if IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)
+#if CONFIG(BOOTBLOCK_CONSOLE)
console_init();
#endif
diff --git a/src/arch/ppc64/include/arch/cpu.h b/src/arch/ppc64/include/arch/cpu.h
index 3238bfb..1e13528 100644
--- a/src/arch/ppc64/include/arch/cpu.h
+++ b/src/arch/ppc64/include/arch/cpu.h
@@ -31,7 +31,7 @@
struct cpu_info {
struct device *cpu;
unsigned long index;
-#if IS_ENABLED(CONFIG_COOP_MULTITASKING)
+#if CONFIG(COOP_MULTITASKING)
struct thread *thread;
#endif
};
diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h
index 4ee580c..547cb76 100644
--- a/src/arch/riscv/include/arch/cpu.h
+++ b/src/arch/riscv/include/arch/cpu.h
@@ -33,7 +33,7 @@
struct cpu_info {
struct device *cpu;
unsigned long index;
-#if IS_ENABLED(CONFIG_COOP_MULTITASKING)
+#if CONFIG(COOP_MULTITASKING)
struct thread *thread;
#endif
};
diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c
index e540828..a5f3fd4 100644
--- a/src/arch/riscv/sbi.c
+++ b/src/arch/riscv/sbi.c
@@ -45,7 +45,7 @@
return 0;
}
-#if IS_ENABLED(CONFIG_CONSOLE_SERIAL)
+#if CONFIG(CONSOLE_SERIAL)
static uintptr_t sbi_console_putchar(uint8_t ch)
{
uart_tx_byte(CONFIG_UART_FOR_CONSOLE, ch);
@@ -86,7 +86,7 @@
ret = sbi_set_timer(arg0);
#endif
break;
-#if IS_ENABLED(CONFIG_CONSOLE_SERIAL)
+#if CONFIG(CONSOLE_SERIAL)
case SBI_CONSOLE_PUTCHAR:
ret = sbi_console_putchar(arg0);
break;
diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c
index 623a6df..486f8e3 100644
--- a/src/arch/x86/acpi.c
+++ b/src/arch/x86/acpi.c
@@ -1066,7 +1066,7 @@
header->checksum = acpi_checksum((void *)bert, header->length);
}
-#if IS_ENABLED(CONFIG_COMMON_FADT)
+#if CONFIG(COMMON_FADT)
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
@@ -1088,11 +1088,11 @@
fadt->x_dsdt_l = (unsigned long)dsdt;
fadt->x_dsdt_h = 0;
- if (IS_ENABLED(CONFIG_SYSTEM_TYPE_CONVERTIBLE) ||
- IS_ENABLED(CONFIG_SYSTEM_TYPE_LAPTOP))
+ if (CONFIG(SYSTEM_TYPE_CONVERTIBLE) ||
+ CONFIG(SYSTEM_TYPE_LAPTOP))
fadt->preferred_pm_profile = PM_MOBILE;
- else if (IS_ENABLED(CONFIG_SYSTEM_TYPE_DETACHABLE) ||
- IS_ENABLED(CONFIG_SYSTEM_TYPE_TABLET))
+ else if (CONFIG(SYSTEM_TYPE_DETACHABLE) ||
+ CONFIG(SYSTEM_TYPE_TABLET))
fadt->preferred_pm_profile = PM_TABLET;
else
fadt->preferred_pm_profile = PM_DESKTOP;
@@ -1256,7 +1256,7 @@
acpi_add_table(rsdp, mcfg);
}
- if (IS_ENABLED(CONFIG_TPM1)) {
+ if (CONFIG(TPM1)) {
printk(BIOS_DEBUG, "ACPI: * TCPA\n");
tcpa = (acpi_tcpa_t *) current;
acpi_create_tcpa(tcpa);
@@ -1267,7 +1267,7 @@
}
}
- if (IS_ENABLED(CONFIG_TPM2)) {
+ if (CONFIG(TPM2)) {
printk(BIOS_DEBUG, "ACPI: * TPM2\n");
tpm2 = (acpi_tpm2_t *) current;
acpi_create_tpm2(tpm2);
diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c
index c62d6f3..c57ba48 100644
--- a/src/arch/x86/acpi_device.c
+++ b/src/arch/x86/acpi_device.c
@@ -19,7 +19,7 @@
#include <arch/acpigen.h>
#include <device/device.h>
#include <device/path.h>
-#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB)
+#if CONFIG(GENERIC_GPIO_LIB)
#include <gpio.h>
#endif
@@ -342,7 +342,7 @@
/* Pin Table, one word for each pin */
for (pin = 0; pin < gpio->pin_count; pin++) {
uint16_t acpi_pin = gpio->pins[pin];
-#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB)
+#if CONFIG(GENERIC_GPIO_LIB)
acpi_pin = gpio_acpi_pin(acpi_pin);
#endif
acpigen_emit_word(acpi_pin);
@@ -352,7 +352,7 @@
acpi_device_fill_from_len(resource_offset, start);
/* Resource Source Name String */
-#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB)
+#if CONFIG(GENERIC_GPIO_LIB)
acpigen_emit_string(gpio->resource ? : gpio_acpi_path(gpio->pins[0]));
#else
acpigen_emit_string(gpio->resource);
diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c
index e455b45..4c57303 100644
--- a/src/arch/x86/acpi_s3.c
+++ b/src/arch/x86/acpi_s3.c
@@ -82,7 +82,7 @@
{
uintptr_t top;
- if (IS_ENABLED(CONFIG_ACPI_HUGE_LOWMEM_BACKUP)) {
+ if (CONFIG(ACPI_HUGE_LOWMEM_BACKUP)) {
base = CONFIG_RAMBASE;
size = HIGH_MEMORY_SAVE;
}
@@ -169,7 +169,7 @@
if (!acpi_s3_resume_allowed())
return;
- if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE))
+ if (CONFIG(RELOCATABLE_RAMSTAGE))
return;
backup_create_or_update(NULL, (uintptr_t)_program,
@@ -194,7 +194,7 @@
return;
}
- if (!IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) {
+ if (!CONFIG(RELOCATABLE_RAMSTAGE)) {
struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME);
if (backup_mem && backup_mem->valid) {
backup_mem->valid = 0;
@@ -224,7 +224,7 @@
void acpi_resume(void *wake_vec)
{
- if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+ if (CONFIG(HAVE_SMI_HANDLER)) {
void *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS);
/* Restore GNVS pointer in SMM if found */
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
index 02f492c..4ead9ea 100644
--- a/src/arch/x86/assembly_entry.S
+++ b/src/arch/x86/assembly_entry.S
@@ -16,7 +16,7 @@
#include <rules.h>
-#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
/*
* This path is for stages that are post bootblock when employing
@@ -43,8 +43,8 @@
sub %edi, %ecx
rep stosl
-#if ((ENV_VERSTAGE && IS_ENABLED(CONFIG_VERSTAGE_DEBUG_SPINLOOP)) \
- || (ENV_ROMSTAGE && IS_ENABLED(CONFIG_ROMSTAGE_DEBUG_SPINLOOP)))
+#if ((ENV_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \
+ || (ENV_ROMSTAGE && CONFIG(ROMSTAGE_DEBUG_SPINLOOP)))
/* Wait for a JTAG debugger to break in and set EBX non-zero */
xor %ebx, %ebx
@@ -55,7 +55,7 @@
#endif
andl $0xfffffff0, %esp
-#if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE)
+#if CONFIG(IDT_IN_EVERY_STAGE)
call exception_init
#endif
call car_stage_entry
@@ -75,7 +75,7 @@
#include <arch/x86/prologue.inc>
#include <cpu/x86/32bit/entry32.inc>
#include <cpu/x86/fpu_enable.inc>
-#if IS_ENABLED(CONFIG_SSE)
+#if CONFIG(SSE)
#include <cpu/x86/sse_enable.inc>
#endif
diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld
index 5a93334..8ccd3e4 100644
--- a/src/arch/x86/bootblock.ld
+++ b/src/arch/x86/bootblock.ld
@@ -17,7 +17,7 @@
#include <cpu/x86/16bit/entry16.ld>
#include <cpu/x86/16bit/reset16.ld>
#include <arch/x86/id.ld>
-#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
#include <cpu/intel/fit/fit.ld>
#endif
diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S
index 4eb36b2..ea55096 100644
--- a/src/arch/x86/bootblock_crt0.S
+++ b/src/arch/x86/bootblock_crt0.S
@@ -32,7 +32,7 @@
#include <cpu/x86/16bit/reset16.inc>
#include <cpu/x86/32bit/entry32.inc>
-#if IS_ENABLED(CONFIG_BOOTBLOCK_DEBUG_SPINLOOP)
+#if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP)
/* Wait for a JTAG debugger to break in and set EBX non-zero */
xor %ebx, %ebx
@@ -44,7 +44,7 @@
bootblock_protected_mode_entry:
-#if !IS_ENABLED(CONFIG_USE_MARCH_586)
+#if !CONFIG(USE_MARCH_586)
/* MMX registers required here */
/* BIST result in eax */
@@ -57,12 +57,12 @@
movd %edx, %mm2
#endif
-#if IS_ENABLED(CONFIG_SSE)
+#if CONFIG(SSE)
enable_sse:
mov %cr4, %eax
or $CR4_OSFXSR, %ax
mov %eax, %cr4
-#endif /* IS_ENABLED(CONFIG_SSE) */
+#endif /* CONFIG(SSE) */
/* We're done. Now it's up to platform-specific code */
jmp bootblock_pre_c_entry
diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S
index bfcc1e61a..02603e9 100644
--- a/src/arch/x86/bootblock_romcc.S
+++ b/src/arch/x86/bootblock_romcc.S
@@ -37,7 +37,7 @@
#include <arch/x86/timestamp.inc>
-#if IS_ENABLED(CONFIG_SSE)
+#if CONFIG(SSE)
#include <cpu/x86/sse_enable.inc>
#endif
diff --git a/src/arch/x86/bootblock_simple.c b/src/arch/x86/bootblock_simple.c
index bf71bca..fc041c8 100644
--- a/src/arch/x86/bootblock_simple.c
+++ b/src/arch/x86/bootblock_simple.c
@@ -22,12 +22,12 @@
bootblock_mainboard_init();
sanitize_cmos();
-#if IS_ENABLED(CONFIG_CMOS_POST)
+#if CONFIG(CMOS_POST)
cmos_post_init();
#endif
}
-#if IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE)
+#if CONFIG(VBOOT_SEPARATE_VERSTAGE)
const char *target1 = "fallback/verstage";
#else
const char *target1 = "fallback/romstage";
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 86147ec..32b848d 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -25,7 +25,7 @@
_stack:
.space (CONFIG_MAX_CPUS+1)*CONFIG_STACK_SIZE
_estack:
-#if IS_ENABLED(CONFIG_COOP_MULTITASKING)
+#if CONFIG(COOP_MULTITASKING)
.global thread_stacks
thread_stacks:
.space CONFIG_STACK_SIZE*CONFIG_NUM_THREADS
@@ -76,7 +76,7 @@
movl $_estack, %esp
andl $(~(CONFIG_STACK_SIZE-1)), %esp
-#if IS_ENABLED(CONFIG_COOP_MULTITASKING)
+#if CONFIG(COOP_MULTITASKING)
/* Push the thread pointer. */
push $0
#endif
@@ -93,7 +93,7 @@
andl $0xFFFFFFF0, %esp
-#if IS_ENABLED(CONFIG_GDB_WAIT)
+#if CONFIG(GDB_WAIT)
call gdb_hw_init
call gdb_stub_breakpoint
#endif
@@ -104,7 +104,7 @@
hlt
jmp .Lhlt
-#if IS_ENABLED(CONFIG_GDB_WAIT)
+#if CONFIG(GDB_WAIT)
.globl gdb_stub_breakpoint
gdb_stub_breakpoint:
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index d6576f7..4637362 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -19,7 +19,7 @@
. = CONFIG_DCACHE_RAM_BASE;
.car.data . (NOLOAD) : {
_car_region_start = . ;
-#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)
+#if CONFIG(PAGING_IN_CACHE_AS_RAM)
/* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB
* aligned when using this option. */
_pagetables = . ;
@@ -28,7 +28,7 @@
#endif
/* Vboot work buffer only needs to be available when verified boot
* starts in bootblock. */
-#if IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)
+#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)
VBOOT2_WORK(., 16K)
#endif
/* Vboot measured boot TCPA log measurements.
@@ -38,7 +38,7 @@
/* Stack for CAR stages. Since it persists across all stages that
* use CAR it can be reused. The chipset/SoC is expected to provide
* the stack size. */
-#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
_car_stack_start = .;
. += CONFIG_DCACHE_BSP_STACK_SIZE;
_car_stack_end = .;
@@ -48,7 +48,7 @@
* multiple stages (romstage and verstage) have a consistent
* link address of these shared objects. */
PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
-#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)
+#if CONFIG(PAGING_IN_CACHE_AS_RAM)
. = ALIGN(32);
/* Page directory pointer table resides here. There are 4 8-byte entries
* totalling 32 bytes that need to be 32-byte aligned. The reason the
@@ -74,7 +74,7 @@
* cbmem console. This is useful for clearing this area on a per-stage
* basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */
_car_global_start = .;
-#if IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION)
+#if CONFIG(NO_CAR_GLOBAL_MIGRATION)
/* Allow global unitialized variables when CAR_GLOBALs are not used. */
*(.bss)
*(.bss.*)
@@ -89,15 +89,15 @@
_car_global_end = .;
_car_relocatable_data_end = .;
-#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) && \
- !IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
+#if CONFIG(NORTHBRIDGE_INTEL_SANDYBRIDGE) && \
+ !CONFIG(USE_NATIVE_RAMINIT)
. = ABSOLUTE(0xff7e1000);
_mrc_pool = .;
. += 0x5000;
_emrc_pool = .;
#endif
-#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
_car_stack_start = .;
_car_stack_end = _car_region_end;
#endif
@@ -113,7 +113,7 @@
.illegal_globals . : {
*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
-#if !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION)
+#if !CONFIG(NO_CAR_GLOBAL_MIGRATION)
*(.bss)
*(.bss.*)
*(.sbss)
@@ -125,9 +125,9 @@
}
_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
-#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)
+#if CONFIG(PAGING_IN_CACHE_AS_RAM)
_bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned");
#endif
-#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
_bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");
#endif
diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c
index 73967e1..648633f 100644
--- a/src/arch/x86/cbmem.c
+++ b/src/arch/x86/cbmem.c
@@ -15,7 +15,7 @@
#include <cbmem.h>
#include <arch/acpi.h>
-#if IS_ENABLED(CONFIG_CBMEM_TOP_BACKUP)
+#if CONFIG(CBMEM_TOP_BACKUP)
void *cbmem_top(void)
{
@@ -39,7 +39,7 @@
/* Something went wrong, our high memory area got wiped */
void cbmem_fail_resume(void)
{
-#if !defined(__PRE_RAM__) && IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if !defined(__PRE_RAM__) && CONFIG(HAVE_ACPI_RESUME)
/* ACPI resume needs to be cleared in the fail-to-recover case, but that
* condition is only handled during ramstage. */
acpi_fail_wakeup();
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
index d070dd9..80d4d0d 100644
--- a/src/arch/x86/cpu.c
+++ b/src/arch/x86/cpu.c
@@ -284,7 +284,7 @@
struct lb_tsc_info *tsc_info;
/* Don't advertise a TSC rate unless it's constant. */
- if (!IS_ENABLED(CONFIG_TSC_CONSTANT_RATE))
+ if (!CONFIG(TSC_CONSTANT_RATE))
return;
freq_khz = tsc_freq_mhz() * 1000;
@@ -302,7 +302,7 @@
void arch_bootstate_coreboot_exit(void)
{
/* APs are already parked by existing infrastructure. */
- if (!IS_ENABLED(CONFIG_PARALLEL_MP_AP_WORK))
+ if (!CONFIG(PARALLEL_MP_AP_WORK))
return;
/* APs are waiting for work. Last thing to do is park them. */
diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c
index 700eb84..b00777a 100644
--- a/src/arch/x86/exception.c
+++ b/src/arch/x86/exception.c
@@ -22,7 +22,7 @@
#include <stdint.h>
#include <string.h>
-#if IS_ENABLED(CONFIG_GDB_STUB)
+#if CONFIG(GDB_STUB)
/* BUFMAX defines the maximum number of characters in inbound/outbound buffers.
* At least NUM_REGBYTES*2 are needed for register packets
@@ -394,7 +394,7 @@
void x86_exception(struct eregs *info)
{
-#if IS_ENABLED(CONFIG_GDB_STUB)
+#if CONFIG(GDB_STUB)
int signo;
memcpy(gdb_stub_registers, info, 8*sizeof(uint32_t));
gdb_stub_registers[PC] = info->eip;
diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S
index 735399b..769a758 100644
--- a/src/arch/x86/exit_car.S
+++ b/src/arch/x86/exit_car.S
@@ -61,7 +61,7 @@
* 0x00: Number of variable MTRRs to clear
*/
-#if IS_ENABLED(CONFIG_SOC_SETS_MSRS)
+#if CONFIG(SOC_SETS_MSRS)
mov %esp, %ebp
/* Need to align stack to 16 bytes at the call instruction. Therefore
diff --git a/src/arch/x86/gdt.c b/src/arch/x86/gdt.c
index 83ab858..c9aec6d 100644
--- a/src/arch/x86/gdt.c
+++ b/src/arch/x86/gdt.c
@@ -40,7 +40,7 @@
struct gdtarg gdtarg;
/* ramstage is already in high memory. No need to use a new gdt. */
- if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE))
+ if (CONFIG(RELOCATABLE_RAMSTAGE))
return;
newgdt = cbmem_find(CBMEM_ID_GDT);
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index 63f3045..f4ed744 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -32,7 +32,7 @@
* The type and enable fields are common in ACPI, but the
* values themselves are hardware implementation defined.
*/
-#if IS_ENABLED(CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES)
+#if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES)
#define SLP_EN (1 << 13)
#define SLP_TYP_SHIFT 10
#define SLP_TYP (7 << SLP_TYP_SHIFT)
@@ -41,7 +41,7 @@
#define SLP_TYP_S3 5
#define SLP_TYP_S4 6
#define SLP_TYP_S5 7
-#elif IS_ENABLED(CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES)
+#elif CONFIG(ACPI_AMD_HARDWARE_SLEEP_VALUES)
#define SLP_EN (1 << 13)
#define SLP_TYP_SHIFT 10
#define SLP_TYP (7 << SLP_TYP_SHIFT)
@@ -776,7 +776,7 @@
void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id);
void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length);
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt);
-#if IS_ENABLED(CONFIG_COMMON_FADT)
+#if CONFIG(COMMON_FADT)
void acpi_fill_fadt(acpi_fadt_t *fadt);
#endif
@@ -885,8 +885,8 @@
ACPI_S5,
};
-#if IS_ENABLED(CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES) \
- || IS_ENABLED(CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES)
+#if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES) \
+ || CONFIG(ACPI_AMD_HARDWARE_SLEEP_VALUES)
/* Given the provided PM1 control register return the ACPI sleep type. */
static inline int acpi_sleep_from_pm1(uint32_t pm1_cnt)
{
@@ -909,7 +909,7 @@
static inline int acpi_s3_resume_allowed(void)
{
- return IS_ENABLED(CONFIG_HAVE_ACPI_RESUME);
+ return CONFIG(HAVE_ACPI_RESUME);
}
/* Return address in reserved memory where to backup low memory
@@ -919,7 +919,7 @@
*/
void *acpi_backup_container(uintptr_t base, size_t size);
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if CONFIG(HAVE_ACPI_RESUME)
#ifdef __PRE_RAM__
static inline int acpi_is_wakeup_s3(void)
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 3ee5cea..b40dd1b 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -188,7 +188,7 @@
struct cpu_info {
struct device *cpu;
unsigned int index;
-#if IS_ENABLED(CONFIG_COOP_MULTITASKING)
+#if CONFIG(COOP_MULTITASKING)
struct thread *thread;
#endif
};
diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h
index 2b74544..9ea1537 100644
--- a/src/arch/x86/include/arch/early_variables.h
+++ b/src/arch/x86/include/arch/early_variables.h
@@ -19,7 +19,7 @@
#include <arch/symbols.h>
#include <stdlib.h>
-#if ENV_CACHE_AS_RAM && !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION)
+#if ENV_CACHE_AS_RAM && !CONFIG(NO_CAR_GLOBAL_MIGRATION)
asm(".section .car.global_data,\"w\",@nobits");
asm(".previous");
#ifdef __clang__
@@ -100,6 +100,6 @@
#define car_get_var(var) (var)
#define car_sync_var(var) (var)
#define car_set_var(var, val) (var) = (val)
-#endif /* ENV_CACHE_AS_RAM && !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION) */
+#endif /* ENV_CACHE_AS_RAM && !CONFIG(NO_CAR_GLOBAL_MIGRATION) */
#endif /* ARCH_EARLY_VARIABLES_H */
diff --git a/src/arch/x86/include/arch/exception.h b/src/arch/x86/include/arch/exception.h
index 08aedef..d71d5a5 100644
--- a/src/arch/x86/include/arch/exception.h
+++ b/src/arch/x86/include/arch/exception.h
@@ -32,7 +32,7 @@
#include <arch/cpu.h>
-#if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE) || ENV_RAMSTAGE
+#if CONFIG(IDT_IN_EVERY_STAGE) || ENV_RAMSTAGE
asmlinkage void exception_init(void);
#else
static inline void exception_init(void) { /* not implemented */ }
diff --git a/src/arch/x86/include/arch/interrupt.h b/src/arch/x86/include/arch/interrupt.h
index 3373e82..086e5bc 100644
--- a/src/arch/x86/include/arch/interrupt.h
+++ b/src/arch/x86/include/arch/interrupt.h
@@ -21,9 +21,9 @@
#include "registers.h"
/* setup interrupt handlers for mainboard */
-#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE)
+#if CONFIG(PCI_OPTION_ROM_RUN_REALMODE)
extern void mainboard_interrupt_handlers(int intXX, int (*intXX_func)(void));
-#elif IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)
+#elif CONFIG(PCI_OPTION_ROM_RUN_YABEL)
#include <device/oprom/yabel/biosemu.h>
#else
static inline void mainboard_interrupt_handlers(int intXX,
diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h
index 3e2129f..017e661 100644
--- a/src/arch/x86/include/arch/pci_io_cfg.h
+++ b/src/arch/x86/include/arch/pci_io_cfg.h
@@ -21,7 +21,7 @@
static __always_inline
unsigned int pci_io_encode_addr(pci_devfn_t dev, unsigned int where)
{
- if (IS_ENABLED(CONFIG_PCI_IO_CFG_EXT)) {
+ if (CONFIG(PCI_IO_CFG_EXT)) {
// seg == 0
return dev >> 4 | (where & 0xff) | ((where & 0xf00) << 16);
} else {
@@ -77,7 +77,7 @@
outl(value, 0xCFC);
}
-#if !IS_ENABLED(CONFIG_MMCONF_SUPPORT)
+#if !CONFIG(MMCONF_SUPPORT)
/* Avoid name collisions as different stages have different signature
* for these functions. The _s_ stands for simple, fundamental IO or
diff --git a/src/arch/x86/include/arch/registers.h b/src/arch/x86/include/arch/registers.h
index 1d3b90a..41275a8 100644
--- a/src/arch/x86/include/arch/registers.h
+++ b/src/arch/x86/include/arch/registers.h
@@ -60,7 +60,7 @@
};
#endif // !ASSEMBLER
-#if IS_ENABLED(CONFIG_COMPILER_LLVM_CLANG)
+#if CONFIG(COMPILER_LLVM_CLANG)
#define ADDR32(opcode) opcode
#else
#define ADDR32(opcode) addr32 opcode
diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h
index 183d726..f918678 100644
--- a/src/arch/x86/include/arch/smp/spinlock.h
+++ b/src/arch/x86/include/arch/smp/spinlock.h
@@ -15,9 +15,9 @@
#define ARCH_SMP_SPINLOCK_H
#if !defined(__PRE_RAM__) \
- || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) \
- || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) \
- || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+ || CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK) \
+ || CONFIG(HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) \
+ || CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
/*
* Your basic SMP spinlocks, allowing only a single CPU anywhere
diff --git a/src/arch/x86/include/cf9_reset.h b/src/arch/x86/include/cf9_reset.h
index c0dcc92..7b44e0f 100644
--- a/src/arch/x86/include/cf9_reset.h
+++ b/src/arch/x86/include/cf9_reset.h
@@ -27,7 +27,7 @@
void do_full_reset(void);
/* Called by functions below before reset. */
-#if IS_ENABLED(CONFIG_HAVE_CF9_RESET_PREPARE)
+#if CONFIG(HAVE_CF9_RESET_PREPARE)
void cf9_reset_prepare(void);
#else
static inline void cf9_reset_prepare(void) {}
diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c
index a396952..34ab202 100644
--- a/src/arch/x86/ioapic.c
+++ b/src/arch/x86/ioapic.c
@@ -103,7 +103,7 @@
ioapic_interrupts = ioapic_interrupt_count(ioapic_base);
- if (IS_ENABLED(CONFIG_IOAPIC_INTERRUPTS_ON_FSB)) {
+ if (CONFIG(IOAPIC_INTERRUPTS_ON_FSB)) {
/*
* For the Pentium 4 and above APICs deliver their interrupts
* on the front side bus, enable that.
@@ -111,7 +111,7 @@
printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n");
io_apic_write(ioapic_base, 0x03,
io_apic_read(ioapic_base, 0x03) | (1 << 0));
- } else if (IS_ENABLED(CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS)) {
+ } else if (CONFIG(IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS)) {
printk(BIOS_DEBUG,
"IOAPIC: Enabling interrupts on APIC serial bus\n");
io_apic_write(ioapic_base, 0x03, 0);
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
index 5831723..8e073f2 100644
--- a/src/arch/x86/memlayout.ld
+++ b/src/arch/x86/memlayout.ld
@@ -62,7 +62,7 @@
#include <cpu/x86/16bit/entry16.ld>
#include <cpu/x86/16bit/reset16.ld>
#include <arch/x86/id.ld>
-#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
#include <cpu/intel/fit/fit.ld>
#endif
#endif /* ENV_BOOTBLOCK */
diff --git a/src/arch/x86/pci_ops_conf1.c b/src/arch/x86/pci_ops_conf1.c
index b1dadc3..7d82507 100644
--- a/src/arch/x86/pci_ops_conf1.c
+++ b/src/arch/x86/pci_ops_conf1.c
@@ -18,7 +18,7 @@
* Functions for accessing PCI configuration space with type 1 accesses
*/
-#if !IS_ENABLED(CONFIG_PCI_IO_CFG_EXT)
+#if !CONFIG(PCI_IO_CFG_EXT)
#define CONF_CMD(dev, where) (0x80000000 | ((dev)->bus->secondary << 16) | \
((dev)->path.pci.devfn << 8) | (where & ~3))
#else
diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c
index f705944..194efb4 100644
--- a/src/arch/x86/pirq_routing.c
+++ b/src/arch/x86/pirq_routing.c
@@ -198,9 +198,9 @@
addr);
memcpy((void *)addr, routing_table, routing_table->size);
printk(BIOS_INFO, "done.\n");
- if (IS_ENABLED(CONFIG_DEBUG_PIRQ))
+ if (CONFIG(DEBUG_PIRQ))
verify_copy_pirq_routing_table(addr, routing_table);
- if (IS_ENABLED(CONFIG_PIRQ_ROUTE))
+ if (CONFIG(PIRQ_ROUTE))
pirq_route_irqs(addr);
return addr + routing_table->size;
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index a36b900..d62487e 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -106,7 +106,7 @@
void postcar_frame_add_romcache(struct postcar_frame *pcf, int type)
{
- if (!IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
+ if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED))
return;
postcar_frame_add_mtrr(pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, type);
}
@@ -151,7 +151,7 @@
finalize_load(rsl.params, pcf->stack);
- if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE))
+ if (!CONFIG(NO_STAGE_CACHE))
stage_cache_add(STAGE_POSTCAR, prog);
}
@@ -162,7 +162,7 @@
postcar_commit_mtrrs(pcf);
- if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE) &&
+ if (!CONFIG(NO_STAGE_CACHE) &&
romstage_handoff_is_resume()) {
stage_cache_load_stage(STAGE_POSTCAR, &prog);
/* This is here to allow platforms to pass different stack
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index fdf8ca1..1d0ced1 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -30,7 +30,7 @@
#include <memory_info.h>
#include <spd.h>
#include <cbmem.h>
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -350,7 +350,7 @@
t->length = len - 2;
t->vendor = smbios_add_string(t->eos, "coreboot");
-#if !IS_ENABLED(CONFIG_CHROMEOS)
+#if !CONFIG(CHROMEOS)
t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date);
t->bios_version = smbios_add_string(t->eos,
@@ -359,12 +359,12 @@
#define SPACES \
" "
t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date);
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
u32 version_offset = (u32)smbios_string_table_len(t->eos);
#endif
t->bios_version = smbios_add_string(t->eos, SPACES);
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
/* SMBIOS offsets start at 1 rather than 0 */
chromeos_get_chromeos_acpi()->vbt10 =
(u32)t->eos + (version_offset - 1);
@@ -390,10 +390,10 @@
BIOS_CHARACTERISTICS_SELECTABLE_BOOT |
BIOS_CHARACTERISTICS_UPGRADEABLE;
- if (IS_ENABLED(CONFIG_CARDBUS_PLUGIN_SUPPORT))
+ if (CONFIG(CARDBUS_PLUGIN_SUPPORT))
t->bios_characteristics |= BIOS_CHARACTERISTICS_PC_CARD;
- if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES))
+ if (CONFIG(HAVE_ACPI_TABLES))
t->bios_characteristics_ext1 = BIOS_EXT1_CHARACTERISTICS_ACPI;
t->bios_characteristics_ext2 = BIOS_EXT2_CHARACTERISTICS_TARGET;
@@ -402,7 +402,7 @@
return len;
}
-#if !IS_ENABLED(CONFIG_SMBIOS_PROVIDED_BY_MOBO)
+#if !CONFIG(SMBIOS_PROVIDED_BY_MOBO)
const char *__weak smbios_mainboard_serial_number(void)
{
@@ -753,7 +753,7 @@
handle++));
update_max(len, max_struct_size, smbios_write_type11(¤t,
&handle));
- if (IS_ENABLED(CONFIG_ELOG))
+ if (CONFIG(ELOG))
update_max(len, max_struct_size,
elog_smbios_write_type15(¤t,handle++));
update_max(len, max_struct_size, smbios_write_type17(¤t,
diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c
index 5319c69..f17fb85 100644
--- a/src/arch/x86/tables.c
+++ b/src/arch/x86/tables.c
@@ -238,17 +238,17 @@
unsigned long rom_table_end = 0xf0000;
/* This table must be between 0x0f0000 and 0x100000 */
- if (IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE))
+ if (CONFIG(GENERATE_PIRQ_TABLE))
rom_table_end = write_pirq_table(rom_table_end);
/* The smp table must be in 0-1K, 639K-640K, or 960K-1M */
- if (IS_ENABLED(CONFIG_GENERATE_MP_TABLE))
+ if (CONFIG(GENERATE_MP_TABLE))
rom_table_end = write_mptable(rom_table_end);
- if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES))
+ if (CONFIG(HAVE_ACPI_TABLES))
rom_table_end = write_acpi_table(rom_table_end);
- if (IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES))
+ if (CONFIG(GENERATE_SMBIOS_TABLES))
rom_table_end = write_smbios_table(rom_table_end);
sz = write_coreboot_forwarding_table(forwarding_table, coreboot_table);
diff --git a/src/arch/x86/timestamp.c b/src/arch/x86/timestamp.c
index b5257c4..5b48c23 100644
--- a/src/arch/x86/timestamp.c
+++ b/src/arch/x86/timestamp.c
@@ -24,7 +24,7 @@
int timestamp_tick_freq_mhz(void)
{
/* Chipsets that have a constant TSC provide this value correctly. */
- if (IS_ENABLED(CONFIG_TSC_CONSTANT_RATE))
+ if (CONFIG(TSC_CONSTANT_RATE))
return tsc_freq_mhz();
/* Filling tick_freq_mhz = 0 in timestamps-table will trigger