*.h: Fix up typos in guarding

Clang complains about this.

Change-Id: I421d6c5daa373d1537e4ac2243438e7f1f6208d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63067
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/arch/riscv/include/arch/barrier.h b/src/arch/riscv/include/arch/barrier.h
index 023e8c3..265aa22 100644
--- a/src/arch/riscv/include/arch/barrier.h
+++ b/src/arch/riscv/include/arch/barrier.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: BSD-3-Clause */
 
-#ifndef __ARCH_BARRIER_H_
+#ifndef __ARCH_BARRIER_H__
 #define __ARCH_BARRIER_H__
 
 static inline void mb(void)  { asm volatile("fence"); }
diff --git a/src/mainboard/intel/dcp847ske/thermal.h b/src/mainboard/intel/dcp847ske/thermal.h
index fcfe695..62bfa1f 100644
--- a/src/mainboard/intel/dcp847ske/thermal.h
+++ b/src/mainboard/intel/dcp847ske/thermal.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #ifndef DCP847SKE_THERMAL_H
-#define DPC847SKE_THERMAL_H
+#define DCP847SKE_THERMAL_H
 
 /* TODO: These should be generated at runtime from
  * MSR_TEMPERATURE_TARGET (0x1a2) */
diff --git a/src/mainboard/intel/dcp847ske/usb.h b/src/mainboard/intel/dcp847ske/usb.h
index 0787ed3..2469309 100644
--- a/src/mainboard/intel/dcp847ske/usb.h
+++ b/src/mainboard/intel/dcp847ske/usb.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #ifndef DCP847SKE_USB_H
-#define DPC847SKE_USB_H
+#define DCP847SKE_USB_H
 
 USB_CONFIG(1, 1, 0), /* back, towards HDMI plugs */
 USB_CONFIG(1, 1, 0), /* back, towards power plug */
diff --git a/src/soc/intel/xeon_sp/include/soc/itss.h b/src/soc/intel/xeon_sp/include/soc/itss.h
index 770a7dd..3be9b8b 100644
--- a/src/soc/intel/xeon_sp/include/soc/itss.h
+++ b/src/soc/intel/xeon_sp/include/soc/itss.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #ifndef SOC_INTEL_XEON_SP_ITSS_H
-#define SOC_INTEL_XEONS_P_ITSS_H
+#define SOC_INTEL_XEON_SP_ITSS_H
 
 #define ITSS_MAX_IRQ	119
 #define IRQS_PER_IPC	32