commit cbf957158806bcd5c733c45baa324559904c609c
author Kyösti Mälkki <kyosti.malkki@gmail.com> Sun Jan 05 08:05:45 2020 +0200
committer Kyösti Mälkki <kyosti.malkki@gmail.com> Thu Jan 09 14:37:33 2020 +0000
tree 89649e264f785ceb76ce223094b3640135a1b920
parent 2a0e3b25ea282491cba9d32a8f35d9a238db83c7

drivers/pc80/rtc: Separate {get|set}_option() prototypes

Long-term plan is to support loading runtime configuration
from SPI flash as an alternative, so move these prototypes
outside pc80/.

Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/northbridge/intel/gm45/igd.c

diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c
index b1ce1be..cfd067e 100644
--- a/src/northbridge/intel/gm45/igd.c
+++ b/src/northbridge/intel/gm45/igd.c
@@ -19,7 +19,7 @@
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <console/console.h>
-#include <pc80/mc146818rtc.h>
+#include <option.h>
 
 #include "gm45.h"
 

src/northbridge/intel/i945/early_init.c

diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 6e650eb..1deca3e 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -21,7 +21,7 @@
 #include <device/pci_def.h>
 #include <cbmem.h>
 #include <romstage_handoff.h>
-#include <pc80/mc146818rtc.h>
+#include <option.h>
 #include <types.h>
 
 #include "i945.h"

src/northbridge/intel/i945/gma.c

diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index d08b77d..98e30e7 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -22,7 +22,7 @@
 #include <device/pci.h>
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
-#include <pc80/mc146818rtc.h>
+#include <option.h>
 #include <edid.h>
 #include <drivers/intel/gma/edid.h>
 #include <drivers/intel/gma/i915.h>

src/northbridge/intel/nehalem/raminit.c

diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 215e9b8..7735522 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -24,7 +24,7 @@
 #include <cbmem.h>
 #include <cf9_reset.h>
 #include <ip_checksum.h>
-#include <pc80/mc146818rtc.h>
+#include <option.h>
 #include <device/pci_def.h>
 #include <device/device.h>
 #include <halt.h>

src/northbridge/intel/pineview/early_init.c

diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c
index b5c5ee0..c3cd380 100644
--- a/src/northbridge/intel/pineview/early_init.c
+++ b/src/northbridge/intel/pineview/early_init.c
@@ -20,7 +20,7 @@
 #include <device/pci.h>
 #include <northbridge/intel/pineview/pineview.h>
 #include <northbridge/intel/pineview/chip.h>
-#include <pc80/mc146818rtc.h>
+#include <option.h>
 #include <types.h>
 
 #define LPC PCI_DEV(0, 0x1f, 0)

src/northbridge/intel/sandybridge/early_init.c

diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 95fc52d..74ae4f5 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -21,7 +21,7 @@
 #include <device/device.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
-#include <pc80/mc146818rtc.h>
+#include <option.h>
 #include <romstage_handoff.h>
 #include <types.h>
 

src/northbridge/intel/x4x/early_init.c

diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index c9d44fc..3520b88 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -22,7 +22,7 @@
 #else
 #include <southbridge/intel/i82801jx/i82801jx.h> /* DEFAULT_PMBASE */
 #endif
-#include <pc80/mc146818rtc.h>
+#include <option.h>
 #include "x4x.h"
 #include <console/console.h>
 #include <romstage_handoff.h>