commit cbe38923d9da5b0f7fb1ccd9696d483b2e63429a
author Martin Roth <martinroth@google.com> Tue Jan 05 19:40:41 2016 -0700
committer Martin Roth <martinroth@google.com> Wed Jan 13 17:52:46 2016 +0100
tree e4260b894c351dfae1ce4c6fab628c3e288b26ed
parent d274c99ad73c60e93ee22e33f4794e47ec3ffb52

northbridge/intel/x4x: clean up includes

- Don't redefine D0F0_PCIEXBAR_LO, use the #define in x4x.h
- Move TPMBASE and TPM32() definitions into iomap.h
- Use "" style include for x4x.h in nortbridge files.
- Move includes of .h files out of x4x.h and into the c files that need
them.
- Protect function definitions in bootblock.

Change-Id: I3fdb579235c5446733a0ffba05fffe1a73381251
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12849
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/northbridge/intel/x4x/bootblock.c

diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c
index 0a8946c..832fa7b 100644
--- a/src/northbridge/intel/x4x/bootblock.c
+++ b/src/northbridge/intel/x4x/bootblock.c
@@ -15,10 +15,8 @@
  */
 
 #include <arch/io.h>
-
-#define D0F0_PCIEXBAR_LO 0x60
-#define TPMBASE 0xfed40000
-#define TPM32(x) *((volatile u32 *)(TPMBASE + x))
+#include "iomap.h"
+#include "x4x.h"
 
 static void bootblock_northbridge_init(void)
 {

src/northbridge/intel/x4x/early_init.c

diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index 1d43e0a..b98c42e 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -16,6 +16,8 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include "iomap.h"
+#include <southbridge/intel/i82801gx/i82801gx.h> /* DEFAULT_PMBASE */
 #include "x4x.h"
 
 void x4x_early_init(void)

src/northbridge/intel/x4x/iomap.h

diff --git a/src/northbridge/intel/x4x/iomap.h b/src/northbridge/intel/x4x/iomap.h
index 34153c1..fc25f9c 100644
--- a/src/northbridge/intel/x4x/iomap.h
+++ b/src/northbridge/intel/x4x/iomap.h
@@ -25,4 +25,7 @@
 #define DEFAULT_EPBAR		0xfed19000	/* 4 KB */
 #define DEFAULT_HECIBAR		0xfed10000
 
+#define TPMBASE 0xfed40000
+#define TPM32(x) *((volatile u32 *)(TPMBASE + x))
+
 #endif /* X4X_IOMAP_H */

src/northbridge/intel/x4x/raminit.c

diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index f5a4e5f..6efdcd3 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -22,7 +22,9 @@
 #include <delay.h>
 #include <halt.h>
 #include <lib.h>
-#include <northbridge/intel/x4x/x4x.h>
+#include "iomap.h"
+#include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */
+#include "x4x.h"
 #include <pc80/mc146818rtc.h>
 #include <spd.h>
 #include <string.h>

src/northbridge/intel/x4x/raminit_ddr2.c

diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c
index 2402321..d77c2c4 100644
--- a/src/northbridge/intel/x4x/raminit_ddr2.c
+++ b/src/northbridge/intel/x4x/raminit_ddr2.c
@@ -20,7 +20,8 @@
 #include <console/console.h>
 #include <commonlib/helpers.h>
 #include <delay.h>
-#include <northbridge/intel/x4x/x4x.h>
+#include "iomap.h"
+#include "x4x.h"
 
 static inline void barrier(void)
 {

src/northbridge/intel/x4x/x4x.h

diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index 89ca931..c226950 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -18,9 +18,6 @@
 #ifndef __NORTHBRIDGE_INTEL_X4X_H__
 #define __NORTHBRIDGE_INTEL_X4X_H__
 
-#include <northbridge/intel/x4x/iomap.h>
-#include <southbridge/intel/i82801gx/i82801gx.h>
-
 /*
  * D0:F0
  */
@@ -307,6 +304,7 @@
         DQ8
 };
 
+#ifndef __BOOTBLOCK__
 void x4x_early_init(void);
 u32 decode_igd_memory_size(u32 gms);
 u32 decode_igd_gtt_size(u32 gsm);
@@ -316,5 +314,5 @@
 
 struct acpi_rsdp;
 unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp);
-
+#endif
 #endif /* __NORTHBRIDGE_INTEL_X4X_H__ */