mb/google/guybrush/var/nipperkin: update USB 2.0 controller Lane Parameter
Enhance USB 2.0 SI by increasing the level of "HS DC Voltage Level"
and "Disconnect Threshold Adjustment" per port:
port#0: COMPDISTUNE0: 0x1->0x5 / TXVREFTUNE0: 0x3->0x9
port#1: COMPDISTUNE0: 0x1->0x5 / TXVREFTUNE0: 0x3->0x9
port#4: COMPDISTUNE0: 0x1->0x6 / TXVREFTUNE0: 0x3->0xE
port#5: COMPDISTUNE0: 0x1->0x5 / TXVREFTUNE0: 0x3->0x9
BUG=b:203049656
BRANCH=guybrush
TEST=1. emerge-guybrush coreboot chromeos-bootimage
2. pass USB eye diagram verification
Change-Id: If5a6563e93bfa6beb529a5593fcc9124ce62d77f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
index c7917ae..f9092a2 100644
--- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
+++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
@@ -27,6 +27,139 @@
end
chip soc/amd/cezanne
+
+ register "usb_phy_custom" = "1"
+ register "usb_phy" = "{
+ /* Left USB C0 Port */
+ .Usb2PhyPort[0] = {
+ .compdstune = 5,
+ .sqrxtune = 3,
+ .txfslstune = 3,
+ .txpreempamptune = 1,
+ .txpreemppulsetune = 0,
+ .txrisetune = 1,
+ .txvreftune = 9,
+ .txhsxvtune = 3,
+ .txrestune = 1,
+ },
+ /* Left USB A0 Port or WWAN */
+ .Usb2PhyPort[1] = {
+ .compdstune = 5,
+ .sqrxtune = 3,
+ .txfslstune = 3,
+ .txpreempamptune = 1,
+ .txpreemppulsetune = 0,
+ .txrisetune = 1,
+ .txvreftune = 9,
+ .txhsxvtune = 3,
+ .txrestune = 1,
+ },
+ /* User facing camera */
+ .Usb2PhyPort[2] = {
+ .compdstune = 1,
+ .sqrxtune = 3,
+ .txfslstune = 3,
+ .txpreempamptune = 2,
+ .txpreemppulsetune = 0,
+ .txrisetune = 2,
+ .txvreftune = 3,
+ .txhsxvtune = 3,
+ .txrestune = 2,
+ },
+ /* World facing camera */
+ .Usb2PhyPort[3] = {
+ .compdstune = 1,
+ .sqrxtune = 3,
+ .txfslstune = 3,
+ .txpreempamptune = 2,
+ .txpreemppulsetune = 0,
+ .txrisetune = 2,
+ .txvreftune = 3,
+ .txhsxvtune = 3,
+ .txrestune = 2,
+ },
+ /* Right USB C1 Port */
+ .Usb2PhyPort[4] = {
+ .compdstune = 6,
+ .sqrxtune = 3,
+ .txfslstune = 3,
+ .txpreempamptune = 1,
+ .txpreemppulsetune = 0,
+ .txrisetune = 1,
+ .txvreftune = 0xe,
+ .txhsxvtune = 3,
+ .txrestune = 1,
+ },
+ /* Right USB A1 Port */
+ .Usb2PhyPort[5] = {
+ .compdstune = 5,
+ .sqrxtune = 3,
+ .txfslstune = 3,
+ .txpreempamptune = 1,
+ .txpreemppulsetune = 0,
+ .txrisetune = 1,
+ .txvreftune = 9,
+ .txhsxvtune = 3,
+ .txrestune = 1,
+ },
+ /* WiFi / Bluetooth */
+ .Usb2PhyPort[6] = {
+ .compdstune = 1,
+ .sqrxtune = 3,
+ .txfslstune = 3,
+ .txpreempamptune = 2,
+ .txpreemppulsetune = 0,
+ .txrisetune = 2,
+ .txvreftune = 3,
+ .txhsxvtune = 3,
+ .txrestune = 2,
+ },
+ /* Smart Card */
+ .Usb2PhyPort[7] = {
+ .compdstune = 1,
+ .sqrxtune = 3,
+ .txfslstune = 3,
+ .txpreempamptune = 2,
+ .txpreemppulsetune = 0,
+ .txrisetune = 2,
+ .txvreftune = 3,
+ .txhsxvtune = 3,
+ .txrestune = 2,
+ },
+ /* Left USB C0 Port */
+ .Usb3PhyPort[0] = {
+ .tx_term_ctrl=2,
+ .rx_term_ctrl=2,
+ .tx_vboost_lvl_en=1,
+ .tx_vboost_lvl=5,
+ },
+ /* Left USB A0 Port or WWAN */
+ .Usb3PhyPort[1] = {
+ .tx_term_ctrl=2,
+ .rx_term_ctrl=2,
+ .tx_vboost_lvl_en=1,
+ .tx_vboost_lvl=5,
+ },
+ /* Right USB C1 Port */
+ .Usb3PhyPort[2] = {
+ .tx_term_ctrl=2,
+ .rx_term_ctrl=2,
+ .tx_vboost_lvl_en=1,
+ .tx_vboost_lvl=5,
+ },
+ /* Right USB A1 Port */
+ .Usb3PhyPort[3] = {
+ .tx_term_ctrl=2,
+ .rx_term_ctrl=2,
+ .tx_vboost_lvl_en=1,
+ .tx_vboost_lvl=5,
+ },
+ .ComboPhyStaticConfig[0] = 0,
+ .ComboPhyStaticConfig[1] = 0,
+ .BatteryChargerEnable = 0,
+ .PhyP3CpmP4Support = 0,
+ }"
+
device domain 0 on
device ref gpp_bridge_2 on
# Required so the NVMe gets placed into D3 when entering S0i3.