sb/intel/i82371eb: Fix 16-bit read/write PCI_COMMAND register
Change-Id: Icecda127a7229c1410c73a6fdd0898430f7eceb2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40809
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index efbfb224..ae35d90 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -27,9 +27,7 @@
/*
* Enable special cycles, needed for soft poweroff.
*/
- reg32 = pci_read_config16(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_SPECIAL;
- pci_write_config16(dev, PCI_COMMAND, reg32);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SPECIAL);
/*
* The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)