util/inteltool: Add more Westmere/Ironlake device IDs
The host bridge PCI device ID can be changed by the firmware. There
is no documentation about it, though. There's 'official' IDs, which
appear in spec updates and Windows drivers, and 'mysterious' IDs,
which Intel doesn't want OSes to know about and thus are not listed.
For the sake of completeness, add the PCI device IDs for Clarkdale.
Though coreboot only supports Arrandale, both of them are Ironlake.
It is possible that the Management Engine handles changing the PCI
device ID, which would not happen when using a broken ME firmware.
Change-Id: I85a48fcf0e0e62f42fe147a5d4e2d557b2143e5b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index dfe8ca6..9a4ab89b 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -81,7 +81,11 @@
/* Host bridges /DRAM controllers integrated in CPUs */
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_0TH_GEN,
"0th generation (Nehalem family) Core Processor" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN,
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D,
+ "1st generation (Westmere family) Core Processor" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M,
+ "1st generation (Westmere family) Core Processor" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048,
"1st generation (Westmere family) Core Processor" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D,
"2nd generation (Sandy Bridge family) Core Processor (Desktop)" },
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index 018e92f..9ed958c 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -346,7 +346,9 @@
/* Intel starts counting these generations with the integration of the DRAM controller */
#define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */
-#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */
+#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D 0x0040 /* Clarkdale (Westmere Desktop) */
+#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M 0x0044 /* Arrandale (Westmere Mobile) */
+#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048 0x0048 /* Unknown Westmere */
#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D 0x0100 /* Sandy Bridge (Desktop) */
#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M 0x0104 /* Sandy Bridge (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3 0x0108 /* Sandy Bridge (Xeon E3) */
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index 2ae331a..3e7d3d7 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -192,7 +192,9 @@
mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
break;
- case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
+ case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D:
+ case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M:
+ case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048:
mchbar_phys = pci_read_long(nb, 0x48);
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */
@@ -266,7 +268,9 @@
switch (nb->device_id)
{
- case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
+ case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D:
+ case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M:
+ case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048:
printf ("clock_speed_index = %x\n", read_500 (0,0x609, 6) >> 1);
dump_timings ();
if (dump_spd_file != NULL)
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index 7303811..32afa71 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -378,7 +378,9 @@
dmi_registers = nehalem_dmi_registers;
size = ARRAY_SIZE(nehalem_dmi_registers);
break;
- case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
+ case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D:
+ case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M:
+ case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048:
dmibar_phys = pci_read_long(nb, 0x68);
dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
dmibar_phys &= 0x0000000ffffff000UL; /* 35:12 */