tree 6f81f87cee70ce2edcbb5e635b44b2a51a8c9980
parent cf544ac1f9a62cc58e3911c23a0b905950a0ff2f
author Duncan Laurie <dlaurie@chromium.org> 1421285420 -0800
committer Stefan Reinauer <stefan.reinauer@coreboot.org> 1428689673 +0200

broadwell: Skip steps when disabling PCIe port

When disabling PCIe ports skip steps if no card is detected.
This prevents the loop from timing out on each empty slot.

BUG=chrome-os-partner:31424
BRANCH=broadwell
TEST=build and boot on samus, check that this code is
no longer timing out when disabling PCIe ports

Change-Id: I84ee0e0e325784b3af06abe70420c07cf6e13ed2
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 4d759e2350dd00ceb7df196ac7008729dc1e4cef
Original-Change-Id: Idd88f0f1191a5465a0d8dcca07b5c3a5c5ca8855
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240851
Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9489
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>