soc/intel/alderlake: Hook up CsPiStartHighinEct UPD
This commit provides option for board to set CsPiStartHighinEct
FSP UPD using a new cs_pi_start_high_in_ect mb_cfg field.
BUG=b:279835630
BRANCH=none
TEST=CsPiStartHighinEct UPD is set properly
Change-Id: I7d0d5f3c782e29fb047ea421e1a5fdfc30bcc26d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h
index bd75636..1d9eaf9 100644
--- a/src/soc/intel/alderlake/include/soc/meminit.h
+++ b/src/soc/intel/alderlake/include/soc/meminit.h
@@ -107,6 +107,10 @@
/* Enable/Disable TxDqDqs Retraining for Lp4/Lp5/DDR */
uint8_t LpDdrDqDqsReTraining;
+
+ /* Enable/Disable Cs Pi Start with High value in Ect */
+ uint8_t cs_pi_start_high_in_ect;
+
};
void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c
index 862a322..2e64e77 100644
--- a/src/soc/intel/alderlake/meminit.c
+++ b/src/soc/intel/alderlake/meminit.c
@@ -240,6 +240,9 @@
bool dq_dqs_auto_detect = false;
FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;
+#if CONFIG(SOC_INTEL_RAPTORLAKE)
+ mem_cfg->CsPiStartHighinEct = mb_cfg->cs_pi_start_high_in_ect;
+#endif
mem_cfg->ECT = mb_cfg->ect;
mem_cfg->UserBd = mb_cfg->UserBd;
set_rcomp_config(mem_cfg, mb_cfg);