tree 342666bf51e850062f672a253dcb5a398e4d8979
parent f0fb3af828b3b457c4487a174440e6f6b6d073ca
author Michał Żygowski <michal.zygowski@3mdeb.com> 1707913408 +0100
committer Felix Singer <service+coreboot-gerrit@felixsinger.de> 1717834706 +0000

soc/alderlake/romstage: Set UsbTcPortEnPreMem UPD based on devicetree

The UsbTcPortEn UPD for FSP-S is being set in ramstage, however the
equivalent FSP-M UPD, the UsbTcPortEnPreMem, was not being set.
Following the Meteor Lake example, set the UsbTcPortEnPreMem UPD
as well for Alder Lake.

Setting this FSP-M UPD will cause FSP to properly program sideband
use BSSB_LSx pins for the enabled Type-C ports. Required for proper
DCI debug and TCSS initialization flow.

Change-Id: If3b79167ec1769ddfb7d28a6c78a3e80bd10afe7
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80500
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>