| commit | f0fb3af828b3b457c4487a174440e6f6b6d073ca | [log] [tgz] |
|---|---|---|
| author | Nicholas Chin <nic.c3.14@gmail.com> | Sat Aug 19 16:19:10 2023 -0600 |
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | Sat Jun 08 06:18:28 2024 +0000 |
| tree | 1e7a56fc4f908f1f5a78a962eadd3ca7d24f528d | |
| parent | ba47ff7197a522f7fd932f6f1dbbe3ad819c7a09 [diff] |
mb/dell: Add Latitude E6430 (Ivy Bridge) Mainboard is QAL80/LA-7781P (UMA). The version with an Nvidia dGPU was not tested. This is based on the autoport output with some manual fixes. The VBT was obtained using `intelvbttool --inlegacy --outvbt data.vbt` while running version A24 (latest version) of the vendor firmware. The flash is 8MiB + 4MiB, and can be easily accessed by removing the keyboard. It can also be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. Working: - Libgfxinit - USB EHCI debug (left side usb port is HCD index 2, middle port on the right side is HCD index 1) with the CH347 - Keyboard - Touchpad/trackpoint - ExpressCard (tested with USB 3.0 card) - Audio - Ethernet - SD card reader - mPCIe WiFi - SeaBIOS 1.16.3 - edk2 (MrChromebox's fork, uefipayload_202309) - Internal flashing using dell-flash-unlock Not working: - S3 suspend: Possibly EC related, DRAM power is getting cut when entering S3 - Physical wireless switch: this triggers an SMI handler in the vendor firmware which sends commands to the EC to enable/disable wireless devices, and has not been reimplemented - Battery reporting: needs ACPI code for the EC - Brightness hotkeys: probably EC related - The system reports that the power button was pressed and shuts down when the CPU hits around 86 degrees Celsius, before the CPU can thermal throttle. Likely EC and possibly PECI related. - Integrated keyboard with upstream GRUB 2.12 payload: Upstream GRUB initializes the 8042 PS/2 controller in a way that is incompatible with how the EC firmware emulates it. GRUB tries to initialize the controller with scan code set 2 without translation, but the EC only ever returns set 1 scan codes to the system and thus is only works as an untranslated set 1 keyboard or a translated set 2 keyboard, regardless of commands to set the scan code. A USB keyboard works fine. Unknown/untested: - Dock - eSATA - TPM - dGPU on non-UMA model - Bluetooth module (not included on my system) [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77444 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot is a Free Software project aimed at replacing the proprietary firmware (BIOS/UEFI) found in most computers. coreboot performs the required hardware initialization to configure the system, then passes control to a different executable, referred to in coreboot as the payload. Most often, the primary function of the payload is to boot the operating system (OS).
With the separation of hardware initialization and later boot logic, coreboot is perfect for a wide variety of situations. It can be used for specialized applications that run directly in the firmware, running operating systems from flash, loading custom bootloaders, or implementing firmware standards, like PC BIOS services or UEFI. This flexibility allows coreboot systems to include only the features necessary in the target application, reducing the amount of code and flash space required.
All source code for coreboot is stored in git. It is downloaded with the command:
git clone https://review.coreboot.org/coreboot.git.
Code reviews are done in the project's Gerrit instance.
The code may be browsed via coreboot's Gitiles instance.
The coreboot project also maintains a mirror of the project on github. This is read-only, as coreboot does not accept github pull requests, but allows browsing and downloading the coreboot source.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://doc.coreboot.org/payloads.html for a list of some of coreboot's supported payloads.
The coreboot project supports a wide range of architectures, chipsets, devices, and mainboards. While not all of these are documented, you can find some information in the Architecture-specific documentation or the SOC-specific documentation.
For details about the specific mainboard devices that coreboot supports, please consult the Mainboard-specific documentation or the Board Status pages.
Releases are currently done by coreboot every quarter. The release archives contain the entire coreboot codebase from the time of the release, along with any external submodules. The submodules containing binaries are separated from the general release archives. All of the packages required to build the coreboot toolchains are also kept at coreboot.org in case the websites change, or those specific packages become unavailable in the future.
All releases are available on the coreboot download page.
Please note that the coreboot releases are best considered as snapshots of the codebase, and do not currently guarantee any sort of extra stability.
The coreboot build, associated utilities and payloads require many additional tools and packages to build. The actual coreboot binary is typically built using a coreboot-controlled toolchain to provide reproducibility across various platforms. It is also possible, though not recommended, to make it directly with your system toolchain. Operating systems and distributions come with an unknown variety of system tools and utilities installed. Because of this, it isn't reasonable to list all the required packages to do a build, but the documentation lists the requirements for a few different Linux distributions.
To see the list of tools and libraries, along with a list of instructions to get started building coreboot, go to the Starting from scratch tutorial page.
That same page goes through how to use QEMU to boot the build and see the output.
Further details on the project, as well as links to documentation and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://doc.coreboot.org/community/forums.html
There are many files in the coreboot tree that we feel are not copyrightable due to a lack of creative content.
"In order to qualify for copyright protection in the United States, a work must satisfy the originality requirement, which has two parts. The work must have “at least a modicum” of creativity, and it must be the independent creation of its author."
https://guides.lib.umich.edu/copyrightbasics/copyrightability
Similar terms apply to other locations.
These uncopyrightable files include:
As non-creative content, these files are in the public domain by default. As such, the coreboot project excludes them from the project's general license even though they may be included in a final binary.
If there are questions or concerns about this policy, please get in touch with the coreboot project via the mailing list.
The copyright on coreboot is owned by quite a large number of individual developers and companies. A list of companies and individuals with known copyright claims is present at the top level of the coreboot source tree in the 'AUTHORS' file. Please check the git history of each of the source files for details.
Because of the way coreboot began, using a significant amount of source code from the Linux kernel, it's licensed the same way as the Linux Kernel, with GNU General Public License (GPL) Version 2. Individual files are licensed under various licenses, though all are compatible with GPLv2. The resulting coreboot image is licensed under the GPL, version 2. All source files should have an SPDX license identifier at the top for clarification.
Files under coreboot/Documentation/ are licensed under CC-BY 4.0 terms. As an exception, files under Documentation/ with a history older than 2017-05-24 might be under different licenses.
Files in the coreboot/src/commonlib/bsd directory are all licensed with the BSD-3-clause license. Many are also dual-licensed GPL-2.0-only or GPL-2.0-or-later. These files are intended to be shared with libpayload or other BSD licensed projects.
The libpayload project contained in coreboot/payloads/libpayload may be licensed as BSD or GPL, depending on the code pulled in during the build process. All GPL source code should be excluded unless the Kconfig option to include it is set.
Since 2017, coreboot has been a member of The Software Freedom Conservancy, a nonprofit organization devoted to ethical technology and driving initiatives to make technology more inclusive. The conservancy acts as coreboot's fiscal sponsor and legal advisor.