nb/intel/haswell: Use <device/dram/ddr3.h>
Change-Id: I353ceb7ab5ec0c82f5e717c856ad7934fcbd03b6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82355
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
index d97ab2a..52bb3b1 100644
--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
@@ -291,20 +291,21 @@
if (!spd_file)
die("SPD data not found.");
- if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) {
+ if (spd_file_len < ((spdi->spd_index + 1) * SPD_SIZE_MAX_DDR3)) {
printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
spdi->spd_index = 0;
}
- if (spd_file_len < SPD_LEN)
+ if (spd_file_len < SPD_SIZE_MAX_DDR3)
die("Missing SPD data.");
/* MRC only uses index 0, but coreboot uses the other indices */
- memcpy(pei_data->spd_data[0], spd_file + (spdi->spd_index * SPD_LEN), SPD_LEN);
+ memcpy(pei_data->spd_data[0], spd_file + (spdi->spd_index * SPD_SIZE_MAX_DDR3),
+ SPD_SIZE_MAX_DDR3);
for (size_t i = 1; i < ARRAY_SIZE(spdi->addresses); i++) {
if (spdi->addresses[i] == SPD_MEMORY_DOWN)
- memcpy(pei_data->spd_data[i], pei_data->spd_data[0], SPD_LEN);
+ memcpy(pei_data->spd_data[i], pei_data->spd_data[0], SPD_SIZE_MAX_DDR3);
}
}