nb/intel/haswell: Use <device/dram/ddr3.h>
Change-Id: I353ceb7ab5ec0c82f5e717c856ad7934fcbd03b6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82355
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/haswell/haswell_mrc/pei_data.h b/src/northbridge/intel/haswell/haswell_mrc/pei_data.h
index c455e17..c8b2e22 100644
--- a/src/northbridge/intel/haswell/haswell_mrc/pei_data.h
+++ b/src/northbridge/intel/haswell/haswell_mrc/pei_data.h
@@ -8,8 +8,6 @@
typedef void (*tx_byte_func)(unsigned char byte);
#define PEI_VERSION 15
-#define SPD_LEN 256
-
#define PEI_USB_OC_PIN_SKIP 8
enum pei_usb2_port_location {
@@ -82,7 +80,7 @@
int usb_xhci_on_resume;
struct pei_usb2_port_setting usb2_ports[16];
struct pei_usb3_port_setting usb3_ports[16];
- uint8_t spd_data[4][SPD_LEN];
+ uint8_t spd_data[4][SPD_SIZE_MAX_DDR3];
tx_byte_func tx_byte;
} __packed;