mb/intel/tglrvp: Enable Intel Speed Shift Technology for Tigerlake RVP

BUG=none
TEST=Build for Tigerlake RVP and boot to OS. Test if following sysfs is populated.
cat /sys/devices/system/cpu/intel_pstate/

Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: Ie3d9691e149a6fbc19c6691896126d04c680fde3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45609
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index a2d297d..84b965e 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -115,6 +115,9 @@
 	register "TcssXhciEn" = "1"
 	register "TcssAuxOri" = "0"
 
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
 	# Enable S0ix
 	register "s0ix_enable" = "1"
 
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index c381d2e..417f23f 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -109,6 +109,9 @@
 	register "TcssXhciEn" = "1"
 	register "TcssAuxOri" = "0"
 
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
 	# Enable S0ix
 	register "s0ix_enable" = "1"