diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index 3908504..39a9369 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -4698,14 +4698,9 @@
 	if (!s3resume)
 		save_timings(&info);
 	if (s3resume && cbmem_wasnot_inited) {
-		u32 reg32;
 		printk(BIOS_ERR, "Failed S3 resume.\n");
 		ram_check_nodie(1 * MiB);
 
-		/* Clear SLP_TYPE.  */
-		reg32 = inl(DEFAULT_PMBASE + 0x04);
-		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
-
 		/* Failed S3 resume, reset to come up cleanly */
 		full_reset();
 	}
diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c
index 6b9f3d0..8d3cfd6 100644
--- a/src/northbridge/intel/ironlake/romstage.c
+++ b/src/northbridge/intel/ironlake/romstage.c
@@ -24,7 +24,6 @@
  */
 void mainboard_romstage_entry(void)
 {
-	u32 reg32;
 	int s3resume = 0;
 	u8 spd_addrmap[4] = {};
 
@@ -60,14 +59,5 @@
 
 	intel_early_me_status();
 
-	if (s3resume) {
-		/*
-		 * Clear SLP_TYPE. This will break stage2 but
-		 * we care for that when we get there.
-		 */
-		reg32 = inl(DEFAULT_PMBASE + 0x04);
-		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
-	}
-
 	romstage_handoff_init(s3resume);
 }