soc/intel/alderlake: Disable Intel TXT based on `INTEL_TXT` config
This patch makes the call into TXT lib in order to disable the TXT
if SoC user haven't selected the `INTEL_TXT` config. Disabling TXT
would be helpful to access VGA framebuffer prior calling into FSP-M.
TEST=Able to perform disable_txt and unlock memory which helped to
access VGA framebuffer prior calling into FSP-M.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9dd7c5492a5f45eef0dd9e836cc2da1844c78919
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71575
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 1b2f695..132e812 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -73,6 +73,7 @@
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select INTEL_GMA_OPREGION_2_1
+ select INTEL_TXT_LIB
select MRC_SETTINGS_PROTECT
select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_2
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index 3ee83bd..b305806 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -19,6 +19,7 @@
#include <cpu/intel/cpu_ids.h>
#include <timestamp.h>
#include <string.h>
+#include <security/intel/txt/txt.h>
#define FSP_SMBIOS_MEMORY_INFO_GUID \
{ \
@@ -135,6 +136,13 @@
smbus_common_init();
/* Initialize HECI interface */
cse_init(HECI1_BASE_ADDRESS);
+ /*
+ * Disable Intel TXT if `CPU is unsupported` or `SoC haven't selected the config`.
+ *
+ * It would help to access VGA framebuffer prior calling into FSP-M.
+ */
+ if (!CONFIG(INTEL_TXT))
+ disable_intel_txt();
if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE))
dbg_feature_cntrl_init();