commit | e01e9b83f901aeb636b1d891c8cd3dbeee0dfcca | [log] [tgz] |
---|---|---|
author | Maximilian Brune <maximilian.brune@9elements.com> | Thu Aug 25 14:22:47 2022 +0200 |
committer | Felix Held <felix-coreboot@felixheld.de> | Mon Aug 29 22:52:36 2022 +0000 |
tree | d92286d8e9207cc3fa8257135fe744671d47ce5c | |
parent | 2dd74906e4830d86a4e4a8113788e8a5c92de2ee [diff] |
mb/prodrive/atlas: Fix SMBUS/SPD addresses Commit 0e7cf3d81d121181a94b6a594b944628c2e5a939 (soc/intel/alderlake: Fix DDR5 channel mapping) fixed a bug in SoC code that messed up DDR5 SPD address mapping. Atlas uses the 0x50/0x52 addresses. However, the SoC code bug required commit 044883615d4471b7a0b883eb8b8224d95faf52af (mb/prodrive/atlas: Update correct SPD address) so that at least some RAM would work. Now that the SoC code bug is fixed, the workaround is no longer needed, so use the correct SPD address mapping. TEST=Boot Atlas and verify that both memory channels work Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I352d8f36eec63cffd3f63ab6e7421db16ca30163 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.