diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 9ac9e22..01abdf8 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <cpu/intel/post_codes.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
@@ -19,7 +20,7 @@
 bootblock_pre_c_entry:
 
 cache_as_ram:
-	post_code(0x20)
+	post_code(POST_BOOTBLOCK_CAR)
 
 	movl	$LAPIC_BASE_MSR, %ecx
 	rdmsr
@@ -52,7 +53,7 @@
 	inc	%ecx
 	dec	%ebx
 	jnz	clear_var_mtrr
-	post_code(0x21)
+	post_code(POST_SOC_SET_DEF_MTRR_TYPE)
 
 	/* Configure the default memory type to uncacheable. */
 	movl	$MTRR_DEF_TYPE_MSR, %ecx
@@ -60,7 +61,7 @@
 	andl	$(~0x00000cff), %eax
 	wrmsr
 
-	post_code(0x22)
+	post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS)
 
 	/* Determine CPU_ADDR_BITS and load PHYSMASK high
 	 * word to %edx.
@@ -104,7 +105,7 @@
 
 bsp_init:
 
-	post_code(0x23)
+	post_code(POST_SOC_BSP_INIT)
 
 	/* Send INIT IPI to all excluding ourself. */
 	movl	LAPIC(ICR), %edi
@@ -118,7 +119,7 @@
 	andl	$LAPIC_ICR_BUSY, %ecx
 	jnz	1b
 
-	post_code(0x24)
+	post_code(POST_SOC_COUNT_CORES)
 
 	movl	$1, %eax
 	cpuid
@@ -153,7 +154,7 @@
 
 hyper_threading_cpu:
 
-	post_code(0x25)
+	post_code(POST_SOC_CPU_HYPER_THREADING)
 
 	/* Send Start IPI to all excluding ourself. */
 	movl	LAPIC(ICR), %edi
@@ -168,7 +169,7 @@
 	andl	$LAPIC_ICR_BUSY, %ecx
 	jnz	1b
 
-	post_code(0x26)
+	post_code(POST_SOC_CPU_SIBLING_DELAY)
 
 	/* Wait for sibling CPU to start. */
 1:	movl	$(MTRR_PHYS_BASE(0)), %ecx
@@ -184,14 +185,14 @@
 
 
 ap_init:
-	post_code(0x27)
+	post_code(POST_SOC_CPU_AP_INIT)
 
 	/* Do not disable cache (so BSP can enable it). */
 	movl	%cr0, %eax
 	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
 	movl	%eax, %cr0
 
-	post_code(0x28)
+	post_code(POST_SOC_SET_MTRR_BASE)
 
 	/* MTRR registers are shared between HT siblings. */
 	movl	$(MTRR_PHYS_BASE(0)), %ecx
@@ -199,7 +200,7 @@
 	xorl	%edx, %edx
 	wrmsr
 
-	post_code(0x29)
+	post_code(POST_SOC_AP_HALT)
 
 ap_halt:
 	cli
@@ -210,7 +211,7 @@
 
 sipi_complete:
 
-	post_code(0x2a)
+	post_code(POST_SOC_SET_CAR_BASE)
 
 	/* Set Cache-as-RAM base address. */
 	movl	$(MTRR_PHYS_BASE(0)), %ecx
@@ -226,7 +227,7 @@
 	orl	$MTRR_PHYS_MASK_VALID, %eax
 	wrmsr
 
-	post_code(0x2b)
+	post_code(POST_SOC_ENABLE_MTRRS)
 
 	/* Enable MTRR. */
 	movl	$MTRR_DEF_TYPE_MSR, %ecx
@@ -269,7 +270,7 @@
 	wrmsr
 no_msr_11e:
 
-	post_code(0x2c)
+	post_code(POST_SOC_ENABLE_CACHE)
 
 	/* Cache the whole rom to fetch microcode updates */
 	movl	$MTRR_PHYS_BASE(1), %ecx
@@ -296,7 +297,7 @@
 	jmp	update_bsp_microcode
 	end_microcode_update:
 #endif
-	post_code(0x2d)
+	post_code(POST_SOC_DISABLE_CACHE)
 	/* Disable caching to change MTRR's. */
 	movl	%cr0, %eax
 	orl	$CR0_CacheDisable, %eax
@@ -336,7 +337,7 @@
 	wrmsr
 
 fill_cache:
-	post_code(0x2e)
+	post_code(POST_SOC_FILL_CACHE)
 	/* Enable cache. */
 	movl	%cr0, %eax
 	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
@@ -379,7 +380,7 @@
 #endif
 
 before_c_entry:
-	post_code(0x2f)
+	post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY)
 	call	bootblock_c_entry_bist
 
 	/* Should never see this postcode */