mb/dell/snb_ivb_latitude: Move E6430 USB config to devicetree
As of commit ee12634872 (nb/sandybridge,sb/bd82x6x: Configure USB from
southbridge devicetree) and earlier commits, the USB port configuration
should be located in the devicetree instead of the mainboard_usb_ports
array, typically located in the boards early_init.c.
TEST=USB ports still function; and the USBIRx, USBPDO, USBOCM1, and
USBOCM2 RCBA registers in the inteltool dump did not change between
an E6430 build before and after the sb/intel/bd82x6x that moved the
usb config to the devicetree.
Change-Id: Ia5aa03a5894a8ef29e863470925a223f52e0ab70
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83006
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6430/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/early_init.c
index b4fd22d..ff83db0 100644
--- a/src/mainboard/dell/snb_ivb_latitude/variants/e6430/early_init.c
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/early_init.c
@@ -5,23 +5,6 @@
#include <ec/dell/mec5035/mec5035.h>
#include <southbridge/intel/bd82x6x/pch.h>
-const struct southbridge_usb_port mainboard_usb_ports[] = {
- { 1, 1, 0 },
- { 1, 1, 0 },
- { 1, 1, 1 },
- { 1, 1, 1 },
- { 1, 0, 2 },
- { 1, 1, 2 },
- { 1, 1, 3 },
- { 1, 1, 3 },
- { 1, 1, 4 },
- { 1, 1, 4 },
- { 1, 1, 5 },
- { 1, 1, 5 },
- { 1, 2, 6 },
- { 1, 2, 6 },
-};
-
void bootblock_mainboard_early_init(void)
{
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb
index 55df5eb..631f404 100644
--- a/src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb
@@ -10,6 +10,22 @@
end
chip southbridge/intel/bd82x6x
+ register "usb_port_config" = "{
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 0, 2 },
+ { 1, 1, 2 },
+ { 1, 1, 3 },
+ { 1, 1, 3 },
+ { 1, 1, 4 },
+ { 1, 1, 4 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 2, 6 },
+ { 1, 2, 6 },
+ }"
device ref xhci on
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"