sb/intel/bd82x6x: Use PCI bitwise ops
Some cases could not be factored out while keeping reproducibility.
Also mark some potential bugs with a FIXME comment, since fixing them
while also keeping the binary unchanged is pretty much impossible.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: Iafe62d952a146bf53a28a1a83b87a3ae31f46720
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c
index e61c60c..895135b 100644
--- a/src/southbridge/intel/bd82x6x/pci.c
+++ b/src/southbridge/intel/bd82x6x/pci.c
@@ -11,30 +11,22 @@
static void pci_init(struct device *dev)
{
u16 reg16;
- u8 reg8;
printk(BIOS_DEBUG, "PCI init.\n");
/* Enable Bus Master */
- reg16 = pci_read_config16(dev, PCI_COMMAND);
- reg16 |= PCI_COMMAND_MASTER;
- pci_write_config16(dev, PCI_COMMAND, reg16);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* This device has no interrupt */
pci_write_config8(dev, INTR, 0xff);
/* disable parity error response and SERR */
- reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
- reg16 &= ~PCI_BRIDGE_CTL_PARITY;
- reg16 &= ~PCI_BRIDGE_CTL_SERR;
- pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
+ pci_and_config16(dev, PCI_BRIDGE_CONTROL,
+ ~(PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR));
/* Master Latency Count must be set to 0x04! */
- reg8 = pci_read_config8(dev, SMLT);
- reg8 &= 0x07;
- reg8 |= (0x04 << 3);
- pci_write_config8(dev, SMLT, reg8);
+ pci_update_config8(dev, SMLT, 0x07, (0x04 << 3));
- /* Clear errors in status registers */
+ /* Clear errors in status registers. FIXME: do we need to do something? */
reg16 = pci_read_config16(dev, PSTS);
//reg16 |= 0xf900;
pci_write_config16(dev, PSTS, reg16);