commit c7b549ec996de4fcb34895d5ed8fd13adb9ba53b
author Garmin Chang <Garmin.Chang@mediatek.com> Mon Sep 12 18:00:21 2022 +0800
committer Felix Held <felix-coreboot@felixheld.de> Wed Sep 14 12:00:06 2022 +0000
tree e33e59da60bdc09386f9b4da91775e805463fdbb
parent 5f9395cbc10ff9db406f0eae77a7d585e1c73b7c

soc/mediatek/mt8188: Change vpp_sel default mux for 4k support

vpp_sel and ethdr_sel are vdosys clock source select mux.

Steps to change to support 4K source:
1. Change vpp_sel source to mainpll_d6 to run at 416MHz.
2. Change ethdr_sel source to univpll_d6 to run at 416MHz.

BUG=b:233720142
TEST=build pass.

Signed-off-by: Garmin Chang <Garmin.Chang@mediatek.com>
Change-Id: I24f133b9b383fd019983cb29a213b47717148e97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67545
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/mediatek/mt8188/pll.c

diff --git a/src/soc/mediatek/mt8188/pll.c b/src/soc/mediatek/mt8188/pll.c
index 735ff47..123d92f 100644
--- a/src/soc/mediatek/mt8188/pll.c
+++ b/src/soc/mediatek/mt8188/pll.c
@@ -256,8 +256,8 @@
 	{ .id = TOP_SCP_SEL, .sel = 5 },			/* 5: mainpll_d4_d2 */
 	{ .id = TOP_BUS_AXIMEM_SEL, .sel = 1 },			/* 1: mainpll_d7_d2 */
 	/* CLK_CFG_1 */
-	{ .id = TOP_VPP_SEL, .sel = 8 },			/* 8: mainpll_d6 */
-	{ .id = TOP_ETHDR_SEL, .sel = 10 },			/* 10: mmpll_d5_d4 */
+	{ .id = TOP_VPP_SEL, .sel = 8 },			/* 8: univpll_d6 */
+	{ .id = TOP_ETHDR_SEL, .sel = 8 },			/* 8: univpll_d6 */
 	{ .id = TOP_IPE_SEL, .sel = 8 },			/* 8: mainpll_d4_d2 */
 	{ .id = TOP_CAM_SEL, .sel = 8 },			/* 8: mainpll_d4_d2 */
 	/* CLK_CFG_2 */