soc/intel/tigerlake: Implement soc_get_pmc_mux_device()
The ChromeOS EC is adding new entries to its USBC.CONx devices (see later
patch), and it needs to get access to the PMC.MUX device so that its
ACPI path can be retrieved. This provides a weak function to return NULL
for all Intel SoCs except for Tiger Lake, which locates the device if it
is found in the devicetree.
Change-Id: I3fe3ef25e9fac8748142f5b1bd870c9bc70b97ff
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40948
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c
index c24898f..84a18e3 100644
--- a/src/soc/intel/tigerlake/pmc.c
+++ b/src/soc/intel/tigerlake/pmc.c
@@ -11,6 +11,7 @@
#include <console/console.h>
#include <device/mmio.h>
#include <device/device.h>
+#include <drivers/intel/pmc_mux/chip.h>
#include <intelblocks/pmc.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/rtc.h>
@@ -123,6 +124,25 @@
dev_path(dev));
}
+/* By default, TGL uses the PMC MUX for all ports, so port_number is unused */
+const struct device *soc_get_pmc_mux_device(int port_number)
+{
+ const struct device *pmc;
+ struct device *child;
+
+ child = NULL;
+ pmc = pcidev_path_on_root(PCH_DEVFN_PMC);
+ if (!pmc || !pmc->link_list)
+ return NULL;
+
+ while ((child = dev_bus_each_child(pmc->link_list, child)) != NULL)
+ if (child->chip_ops == &drivers_intel_pmc_mux_ops)
+ break;
+
+ /* child will either be the correct device or NULL if not found */
+ return child;
+}
+
struct device_operations pmc_ops = {
.read_resources = soc_pmc_read_resources,
.set_resources = noop_set_resources,