soc/rockchip/rk3399/sdram: Add phy_ctrl_reset
Add support for resetting PHY PCTRL for both channel 0 and 1.
On the ROCKPro64 board this allows getting past a pctl_cfg() failure.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I9f807e318ffc63c568d04518c3edd02c1064e185
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50890
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c
index 89463aa..9490c0c 100644
--- a/src/soc/rockchip/rk3399/sdram.c
+++ b/src/soc/rockchip/rk3399/sdram.c
@@ -100,6 +100,18 @@
}
}
+static void phy_pctrl_reset(u32 channel)
+{
+ rkclk_ddr_reset(channel, 1, 1);
+ udelay(10);
+
+ rkclk_ddr_reset(channel, 1, 0);
+ udelay(10);
+
+ rkclk_ddr_reset(channel, 0, 0);
+ udelay(10);
+}
+
static void phy_dll_bypass_set(u32 channel,
struct rk3399_ddr_publ_regs *ddr_publ_regs, u32 freq)
{
@@ -1083,6 +1095,7 @@
rkclk_configure_ddr(ddr_freq);
for (channel = 0; channel < 2; channel++) {
+ phy_pctrl_reset(channel);
phy_dll_bypass_set(channel, rk3399_ddr_publ[channel], ddr_freq);
if (channel >= params->num_channels)