diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c
index c36044f..053815b 100644
--- a/src/northbridge/intel/i945/acpi.c
+++ b/src/northbridge/intel/i945/acpi.c
@@ -29,7 +29,7 @@
 	u32 pciexbar_reg;
 	int max_buses;
 
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	dev = pcidev_on_root(0, 0);
 	if (!dev)
 		return current;
 
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 749d07b..7a2a489 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -73,7 +73,7 @@
 	/*
 	 * The Video BIOS places the GTT right below top of memory.
 	 */
-	tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24;
+	tom = pci_read_config8(pcidev_on_root(0, 0), TOLUD) << 24;
 	PGETBL_save = tom - 256 * KiB;
 	PGETBL_save |= PGETBL_ENABLED;
 	PGETBL_save |= 2; /* set GTT to 256kb */
@@ -357,7 +357,7 @@
 
 	/* Setup GTT.  */
 
-	reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
+	reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC);
 	uma_size = 0;
 	if (!(reg16 & 2)) {
 		uma_size = decode_igd_memory_size((reg16 >> 4) & 7);
@@ -536,7 +536,7 @@
 
 	/* Set up GTT.  */
 
-	reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
+	reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC);
 	uma_size = 0;
 	if (!(reg16 & 2)) {
 		uma_size = decode_igd_memory_size((reg16 >> 4) & 7);
@@ -725,7 +725,7 @@
    be re-enabled later. */
 static void gma_func0_disable(struct device *dev)
 {
-	struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0));
+	struct device *dev_host = pcidev_on_root(0x0, 0);
 
 	pci_write_config16(dev, GCFC, 0xa00);
 	pci_write_config16(dev_host, GGC, (1 << 1));
@@ -768,7 +768,7 @@
 const struct i915_gpu_controller_info *
 intel_gma_get_controller_info(void)
 {
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2, 0));
+	struct device *dev = pcidev_on_root(0x2, 0);
 	if (!dev)
 		return NULL;
 	struct northbridge_intel_i945_config *chip = dev->chip_info;
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index ef3c59c..2b51b5e 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -34,7 +34,7 @@
 
 	*base = 0;
 
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	dev = pcidev_on_root(0, 0);
 	if (!dev)
 		return 0;
 
@@ -76,16 +76,16 @@
 	printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm);
 
 	printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n",
-		    pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), BSM));
+		    pci_read_config32(pcidev_on_root(2, 0), BSM));
 
-	tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD);
+	tolud = pci_read_config8(pcidev_on_root(0, 0), TOLUD);
 	printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08x\n", tolud << 24);
 
 	tomk = tolud << 14;
 	tomk_stolen = tomk;
 
 	/* Note: subtract IGD device and TSEG */
-	reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
+	reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC);
 	if (!(reg16 & 2)) {
 		printk(BIOS_DEBUG, "IGD decoded, subtracting ");
 		int uma_size = decode_igd_memory_size((reg16 >> 4) & 7);
@@ -98,8 +98,8 @@
 		uma_memory_size = uma_size * 1024ULL;
 	}
 
-	tseg_sizek = decode_tseg_size(pci_read_config8(dev_find_slot(0,
-					PCI_DEVFN(0, 0)), ESMRAMC)) >> 10;
+	tseg_sizek = decode_tseg_size(pci_read_config8(pcidev_on_root(0, 0),
+							ESMRAMC)) >> 10;
 	printk(BIOS_DEBUG, "TSEG decoded, subtracting %dM\n", tseg_sizek >> 10);
 	tomk_stolen -= tseg_sizek;
 	tseg_memory_base = tomk_stolen * 1024ULL;
@@ -157,7 +157,7 @@
 
 void northbridge_write_smram(u8 smram)
 {
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	struct device *dev = pcidev_on_root(0, 0);
 
 	if (dev == NULL)
 		die("could not find pci 00:00.0!\n");
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 5f06b7d..64c87da 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -1219,7 +1219,7 @@
 	tom = tolud >> 3;
 
 	/* Limit the value of TOLUD to leave some space for PCI memory. */
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	dev = pcidev_on_root(0, 0);
 	if (dev)
 		cfg = dev->chip_info;