mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant
Tested with SeaBIOS as a payload, booting Arch Linux with
a Linux kernel. The new code is based on autoport and the
existing GA-H61M-S2PV code.
The GA-H61M-S2PV has been boot-tested too, it still boots.
Working:
- S3 suspend/resume
- USB ports and headers (Intel USB2 and EtronTech USB3)
- Gigabit Ethernet
- Integrated DVI/VGA graphics (libgfxinit)
- PCIe x16 graphics
- PCIe x1 ports
- PS/2 port with a keyboard
- SATA controllers (Intel SATA2 and Marvell SATA3)
- User-space fan control (fancontrol on Linux)
- Native raminit (4+4GB DDR3-1333)
- flashrom, using the internal programmer. Tested with coreboot,
as well as with the vendor firmware. Backup chip is untested.
Untested:
- VGA BIOS for integrated graphics init
- Audio: Only front/read outputs has been tested.
- Non-Linux OSes
- ACPI thermal zone and OS-independent fan control
Not working:
- Default IFD defines the BIOS region as the entire flash chip.
Using 'flashrom --ifd -i bios' is asking for a failed flash!
Change-Id: I37928de158bb8fbb47fbda5d1ccd4efba7edab26
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig
index 5e46365..62d7f40 100644
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig
@@ -13,7 +13,7 @@
## GNU General Public License for more details.
##
-if BOARD_GIGABYTE_GA_H61M_S2PV
+if BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61MA_D3V
config BOARD_SPECIFIC_OPTIONS
def_bool y
@@ -31,21 +31,36 @@
select INTEL_GMA_HAVE_VBT
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
+ select NO_UART_ON_SUPERIO if BOARD_GIGABYTE_GA_H61MA_D3V
config MAINBOARD_DIR
string
default "gigabyte/ga-h61m-s2pv"
+config VARIANT_DIR
+ string
+ default "ga-h61m-s2pv" if BOARD_GIGABYTE_GA_H61M_S2PV
+ default "ga-h61ma-d3v" if BOARD_GIGABYTE_GA_H61MA_D3V
+
config MAINBOARD_PART_NUMBER
string
- default "GA-H61M-S2PV"
+ default "GA-H61M-S2PV" if BOARD_GIGABYTE_GA_H61M_S2PV
+ default "GA-H61MA-D3V" if BOARD_GIGABYTE_GA_H61MA_D3V
+
+config DEVICETREE
+ string
+ default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
config MAX_CPUS
int
default 8
+# Override the default variant behavior, since the data.vbt is the same
+config INTEL_GMA_VBT_FILE
+ default "src/mainboard/$(MAINBOARDDIR)/data.vbt"
+
config USBDEBUG_HCD_INDEX # Bottom left port seen from rear
int
default 2
-endif # BOARD_GIGABYTE_GA_H61M_S2PV
+endif # BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61MA_D3V
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name
index 04da3f0..83b5803 100644
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name
@@ -1,2 +1,5 @@
config BOARD_GIGABYTE_GA_H61M_S2PV
bool "GA-H61M-S2PV"
+
+config BOARD_GIGABYTE_GA_H61MA_D3V
+ bool "GA-H61MA-D3V"
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc b/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc
index ea035d3..fe7cc81 100644
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc
@@ -1,3 +1,4 @@
-romstage-y += gpio.c
+romstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c
index 15a2b01..e69de29 100644
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c
@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
- 0x10ec0887, /* Codec Vendor / Device ID: Realtek */
- 0x1458a002, /* Subsystem ID */
-
- 0x0000000f, /* Number of 4 dword sets */
- /* NID 0x01: Subsystem ID. */
- AZALIA_SUBVENDOR(0x2, 0x1458a002),
-
- /* NID 0x11. */
- AZALIA_PIN_CFG(0x2, 0x11, 0x411111f0),
-
- /* NID 0x12. */
- AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0),
-
- /* NID 0x14. */
- AZALIA_PIN_CFG(0x2, 0x14, 0x01014410),
-
- /* NID 0x15. */
- AZALIA_PIN_CFG(0x2, 0x15, 0x411111f0),
-
- /* NID 0x16. */
- AZALIA_PIN_CFG(0x2, 0x16, 0x411111f0),
-
- /* NID 0x17. */
- AZALIA_PIN_CFG(0x2, 0x17, 0x411111f0),
-
- /* NID 0x18. */
- AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50),
-
- /* NID 0x19. */
- AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60),
-
- /* NID 0x1a. */
- AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f),
-
- /* NID 0x1b. */
- AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20),
-
- /* NID 0x1c. */
- AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0),
-
- /* NID 0x1d. */
- AZALIA_PIN_CFG(0x2, 0x1d, 0x4004c601),
-
- /* NID 0x1e. */
- AZALIA_PIN_CFG(0x2, 0x1e, 0x411111f0),
-
- /* NID 0x1f. */
- AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0),
-};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
index 7154cc9..27fbb2ccc 100644
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
@@ -25,10 +25,15 @@
void pch_enable_lpc(void)
{
- pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
- CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
+ if (CONFIG(BOARD_GIGABYTE_GA_H61M_S2PV)) {
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
+ CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
+ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
+ } else if (CONFIG(BOARD_GIGABYTE_GA_H61MA_D3V)) {
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
+ CNF1_LPC_EN);
+ }
}
void mainboard_rcba_config(void)
@@ -58,8 +63,10 @@
void mainboard_config_superio(void)
{
- /* Enable serial port */
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ if (!CONFIG(NO_UART_ON_SUPERIO)) {
+ /* Enable serial port */
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ }
/* Disable SIO WDT which kicks in DualBIOS */
ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E);
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb
similarity index 100%
rename from src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb
rename to src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/gpio.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c
similarity index 100%
rename from src/mainboard/gigabyte/ga-h61m-s2pv/gpio.c
rename to src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c
new file mode 100644
index 0000000..93c7e11
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0887, /* Realtek ALC887 */
+ 0x1458a002, /* Subsystem ID */
+ 0x0000000f, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0x2, 0x1458a002),
+ AZALIA_PIN_CFG(0x2, 0x11, 0x411111f0),
+ AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0),
+ AZALIA_PIN_CFG(0x2, 0x14, 0x01014410),
+ AZALIA_PIN_CFG(0x2, 0x15, 0x411111f0),
+ AZALIA_PIN_CFG(0x2, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0x2, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50),
+ AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60),
+ AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f),
+ AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20),
+ AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0),
+ AZALIA_PIN_CFG(0x2, 0x1d, 0x4004c601),
+ AZALIA_PIN_CFG(0x2, 0x1e, 0x411111f0),
+ AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb
new file mode 100644
index 0000000..22d483e
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb
@@ -0,0 +1,101 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Angel Pons <th3fanbus@gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/sandybridge
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+ register "gfx.ndid" = "3"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/model_206ax
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0x0 on end
+ device lapic 0xacac off end
+ end
+ end
+ register "pci_mmio_size" = "2048"
+ device domain 0x0 on
+ subsystemid 0x1458 0x5001 inherit
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on end # PCIe Bridge for discrete graphics
+ device pci 02.0 on end # Internal graphics
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "gen1_dec" = "0x003c0a01"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x33"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio Audio controller
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 on end # PCIe Port #2
+ device pci 1c.2 on end # PCIe Port #3
+ device pci 1c.3 on end # PCIe Port #4
+ device pci 1c.4 on end # PCIe Port #5
+ device pci 1c.5 on end # PCIe Port #6
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on # LPC bridge
+ chip superio/ite/it8728f
+ device pnp 2e.0 off end # Floppy
+ device pnp 2e.1 off end # COM1
+ device pnp 2e.2 off end # COM2
+ device pnp 2e.3 off end # Parallel port
+ device pnp 2e.4 on # Environment Controller
+ io 0x60 = 0x0a30
+ io 0x62 = 0x0a20
+ irq 0x70 = 9
+ irq 0xf2 = 0x40
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0xf0 = 0x08
+ end
+ device pnp 2e.6 on # Mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 on # GPIO
+ irq 0x25 = 0x40
+ irq 0x26 = 0xf7
+ irq 0x27 = 0x10
+ irq 0x2c = 0x80
+ io 0x60 = 0x0000
+ io 0x62 = 0x0a00
+ io 0x64 = 0x0000
+ irq 0x73 = 0x00
+ irq 0xcb = 0x00
+ irq 0xf0 = 0x10
+ irq 0xf1 = 0x40
+ irq 0xf6 = 0x1c
+ end
+ device pnp 2e.a off end # CIR
+ end
+ end
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 on end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c
new file mode 100644
index 0000000..b717374
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c
@@ -0,0 +1,205 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_NATIVE,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_HIGH,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio24 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_NATIVE,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_NATIVE,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_NATIVE,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_HIGH,
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio35 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c
new file mode 100644
index 0000000..e160538
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Angel Pons <th3fanbus@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0887, /* Realtek ALC887 */
+ 0x1458a002, /* Subsystem ID */
+ 0x0000000f, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0x2, 0x1458a002),
+ AZALIA_PIN_CFG(0x2, 0x11, 0x411110f0),
+ AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0),
+ AZALIA_PIN_CFG(0x2, 0x14, 0x01014410),
+ AZALIA_PIN_CFG(0x2, 0x15, 0x411111f0),
+ AZALIA_PIN_CFG(0x2, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0x2, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50),
+ AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60),
+ AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f),
+ AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20),
+ AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0),
+ AZALIA_PIN_CFG(0x2, 0x1d, 0x4004c601),
+ AZALIA_PIN_CFG(0x2, 0x1e, 0x411111f0),
+ AZALIA_PIN_CFG(0x2, 0x1f, 0x41c46060),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;