diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index c0cf683..ac175c4 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -89,6 +89,7 @@
 	select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
 	select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
 	select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU
+	select CR50_USE_LONG_INTERRUPT_PULSES if TPM_GOOGLE_CR50
 
 config MAX_CPUS
 	int
@@ -223,11 +224,6 @@
 	hex
 	default 0x7fff
 
-# Tiger Lake SoC requires at least 100us interrupt pulses in order to guarantee detection
-# in all low power states.  Cr50 TPM, if used, needs to be told to generate longer pulses.
-config TPM_CR50
-	select CR50_USE_LONG_INTERRUPT_PULSES
-
 config VBT_DATA_SIZE_KB
 	int
 	default 9