tpm: Refactor TPM Kconfig dimensions
Break TPM related Kconfig into the following dimensions:
TPM transport support:
config CRB_TPM
config I2C_TPM
config SPI_TPM
config MEMORY_MAPPED_TPM (new)
TPM brand, not defining any of these is valid, and result in "generic" support:
config TPM_ATMEL (new)
config TPM_GOOGLE (new)
config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE)
config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE)
What protocol the TPM chip supports:
config MAINBOARD_HAS_TPM1
config MAINBOARD_HAS_TPM2
What the user chooses to compile (restricted by the above):
config NO_TPM
config TPM1
config TPM2
The following Kconfigs will be replaced as indicated:
config TPM_CR50 -> TPM_GOOGLE
config MAINBOARD_HAS_CRB_TPM -> CRB_TPM
config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL
config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE
config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM
config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 08ddfa4..b2235f8 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -150,10 +150,10 @@
config TPM_ON_FAST_SPI
bool
default n
- depends on MAINBOARD_HAS_LPC_TPM
+ depends on MEMORY_MAPPED_TPM
help
- TPM part is conntected on Fast SPI interface, but the LPC MMIO
- TPM transactions are decoded and serialized over the SPI interface.
+ TPM part is conntected on Fast SPI interface and is mapped to the
+ linear address space.
config PCR_BASE_ADDRESS
hex
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index ad987dd..43fc2f8 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -20,11 +20,7 @@
ramstage-y += vbt.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c
-bootblock-$(CONFIG_TPM_CR50) += tpm_tis.c
-verstage-$(CONFIG_TPM_CR50) += tpm_tis.c
-romstage-$(CONFIG_TPM_CR50) += tpm_tis.c
-ramstage-$(CONFIG_TPM_CR50) += tpm_tis.c
-postcar-$(CONFIG_TPM_CR50) += tpm_tis.c
+all-$(CONFIG_TPM_GOOGLE) += tpm_tis.c
romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_RESET) += fsp_reset.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_FSP_RESET) += fsp_reset.c
diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl
index 36d4932..1ca6232 100644
--- a/src/soc/intel/skylake/acpi/systemagent.asl
+++ b/src/soc/intel/skylake/acpi/systemagent.asl
@@ -171,7 +171,7 @@
0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff,
0x00000000, PCH_PRESERVED_BASE_SIZE)
-#if !CONFIG(TPM_CR50)
+#if !CONFIG(TPM_GOOGLE)
/* TPM Area (0xfed40000-0xfed44fff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index c0cf683..ac175c4 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -89,6 +89,7 @@
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU
+ select CR50_USE_LONG_INTERRUPT_PULSES if TPM_GOOGLE_CR50
config MAX_CPUS
int
@@ -223,11 +224,6 @@
hex
default 0x7fff
-# Tiger Lake SoC requires at least 100us interrupt pulses in order to guarantee detection
-# in all low power states. Cr50 TPM, if used, needs to be told to generate longer pulses.
-config TPM_CR50
- select CR50_USE_LONG_INTERRUPT_PULSES
-
config VBT_DATA_SIZE_KB
int
default 9