cpu/intel/car: Prepare for C_ENVIRONMENT_BOOTBLOCK
Pass timestamps and BIST to romstage using the same signature
as C_ENVIRONMENT_BOOTBLOCK will.
Change-Id: Ic90da6b1b5ac3b56c69b593ba447ed8e05c8a4e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
index 9a433d6..981b12d 100644
--- a/src/cpu/intel/car/core2/cache_as_ram.S
+++ b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -22,11 +22,12 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+.global bootblock_pre_c_entry
+
.code32
_cache_as_ram_setup:
- /* Save the BIST result. */
- movl %eax, %ebp
+bootblock_pre_c_entry:
cache_as_ram:
post_code(0x20)
@@ -167,22 +168,24 @@
movl %eax, %cr0
/* Setup the stack. */
- movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
- movl %eax, %esp
- /* Align the stack 16 bytes */
+ mov $_car_stack_end, %esp
+
+ /* Need to align stack to 16 bytes at call instruction. Account for
+ the pushes below. */
andl $0xfffffff0, %esp
- /* Account for pushing the BIST result */
- subl $12, %esp
+ subl $4, %esp
- /* Restore the BIST result. */
- movl %ebp, %eax
- movl %esp, %ebp
- pushl %eax
+ /* push TSC and BIST to stack */
+ movd %mm0, %eax
+ pushl %eax /* BIST */
+ movd %mm2, %eax
+ pushl %eax /* tsc[63:32] */
+ movd %mm1, %eax
+ pushl %eax /* tsc[31:0] */
-before_romstage:
+before_c_entry:
post_code(0x29)
- /* Call romstage.c main function. */
- call romstage_main
+ call bootblock_c_entry_bist
/* Should never see this postcode */
post_code(POST_DEAD_CODE)
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index 163f4b4..4ac6d29 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -25,11 +25,12 @@
#define NoEvictMod_MSR 0x2e0
+.global bootblock_pre_c_entry
+
.code32
_cache_as_ram_setup:
- /* Save the BIST result. */
- movl %eax, %ebp
+bootblock_pre_c_entry:
cache_as_ram:
post_code(0x20)
@@ -171,23 +172,24 @@
movl %eax, %cr0
/* Setup the stack. */
- movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
- movl %eax, %esp
+ mov $_car_stack_end, %esp
- /* Align the stack 16 bytes */
+ /* Need to align stack to 16 bytes at call instruction. Account for
+ the pushes below. */
andl $0xfffffff0, %esp
- /* Account for pushing the BIST result */
- subl $12, %esp
+ subl $4, %esp
- /* Restore the BIST result. */
- movl %ebp, %eax
- movl %esp, %ebp
- pushl %eax
+ /* push TSC and BIST to stack */
+ movd %mm0, %eax
+ pushl %eax /* BIST */
+ movd %mm2, %eax
+ pushl %eax /* tsc[63:32] */
+ movd %mm1, %eax
+ pushl %eax /* tsc[31:0] */
-before_romstage:
+before_c_entry:
post_code(0x29)
- /* Call romstage.c main function. */
- call romstage_main
+ call bootblock_c_entry_bist
/* Should never see this postcode */
post_code(POST_DEAD_CODE)
diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S
index 121d169..2809131 100644
--- a/src/cpu/intel/car/p3/cache_as_ram.S
+++ b/src/cpu/intel/car/p3/cache_as_ram.S
@@ -23,11 +23,12 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+.global bootblock_pre_c_entry
+
.code32
_cache_as_ram_setup:
- /* Save the BIST result. */
- movl %eax, %ebp
+bootblock_pre_c_entry:
cache_as_ram:
post_code(0x20)
@@ -156,18 +157,24 @@
movl %eax, %cr0
/* Setup the stack. */
- movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
- movl %eax, %esp
+ mov $_car_stack_end, %esp
- /* Restore the BIST result. */
- movl %ebp, %eax
- movl %esp, %ebp
- pushl %eax
+ /* Need to align stack to 16 bytes at call instruction. Account for
+ the pushes below. */
+ andl $0xfffffff0, %esp
+ subl $4, %esp
-before_romstage:
- post_code(0x2f)
- /* Call romstage.c main function. */
- call romstage_main
+ /* push TSC and BIST to stack */
+ movd %mm0, %eax
+ pushl %eax /* BIST */
+ movd %mm2, %eax
+ pushl %eax /* tsc[63:32] */
+ movd %mm1, %eax
+ pushl %eax /* tsc[31:0] */
+
+before_c_entry:
+ post_code(0x29)
+ call bootblock_c_entry_bist
/* Should never see this postcode */
post_code(POST_DEAD_CODE)
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index eb5e490..8587ea5 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -28,11 +28,12 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+.global bootblock_pre_c_entry
+
.code32
_cache_as_ram_setup:
- /* Save the BIST result. */
- movl %eax, %ebp
+bootblock_pre_c_entry:
cache_as_ram:
post_code(0x20)
@@ -353,22 +354,24 @@
movl %eax, %cr0
/* Setup the stack. */
- movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
- movl %eax, %esp
- /* Align the stack 16 bytes */
+ mov $_car_stack_end, %esp
+
+ /* Need to align stack to 16 bytes at call instruction. Account for
+ the pushes below. */
andl $0xfffffff0, %esp
- /* Account for pushing the BIST result */
- subl $12, %esp
+ subl $4, %esp
- /* Restore the BIST result. */
- movl %ebp, %eax
- movl %esp, %ebp
- pushl %eax
+ /* push TSC and BIST to stack */
+ movd %mm0, %eax
+ pushl %eax /* BIST */
+ movd %mm2, %eax
+ pushl %eax /* tsc[63:32] */
+ movd %mm1, %eax
+ pushl %eax /* tsc[31:0] */
-before_romstage:
+before_c_entry:
post_code(0x2f)
- /* Call romstage.c main function. */
- call romstage_main
+ call bootblock_c_entry_bist
/* Should never see this postcode */
post_code(POST_DEAD_CODE)
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index e21ea46..b9d787f 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -11,6 +11,7 @@
* GNU General Public License for more details.
*/
+#include <bootblock_common.h>
#include <console/console.h>
#include <cpu/intel/romstage.h>
#include <cpu/x86/mtrr.h>
@@ -19,7 +20,7 @@
#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000
-asmlinkage void *romstage_main(unsigned long bist)
+static void romstage_main(unsigned long bist)
{
int i;
const int num_guards = 4;
@@ -50,7 +51,12 @@
}
platform_enter_postcar();
+}
- /* We do not return. */
- return NULL;
+/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
+ * keeping changes in cache_as_ram.S easy to manage.
+ */
+asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
+{
+ romstage_main(bist);
}
diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h
index 726a184..47cd169 100644
--- a/src/include/cpu/intel/romstage.h
+++ b/src/include/cpu/intel/romstage.h
@@ -7,8 +7,4 @@
void platform_enter_postcar(void);
-/* romstage_main is called from the cache-as-ram assembly file to prepare
- * CAR stack guards.*/
-asmlinkage void *romstage_main(unsigned long bist);
-
#endif /* _CPU_INTEL_ROMSTAGE_H */
diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h
index ac0f03b..b65c680 100644
--- a/src/soc/intel/baytrail/include/soc/romstage.h
+++ b/src/soc/intel/baytrail/include/soc/romstage.h
@@ -31,8 +31,7 @@
void mainboard_romstage_entry(struct romstage_params *params);
void romstage_common(struct romstage_params *params);
-void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_lo,
- uint32_t tsc_high);
+
void raminit(struct mrc_params *mp, int prev_sleep_state);
void gfx_init(void);
void tco_disable(void);
diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc
index 8602237d..4326636 100644
--- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc
+++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc
@@ -176,23 +176,24 @@
post_code(0x29)
/* Setup the stack. */
- movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
- movl %eax, %esp
+ mov $_car_stack_end, %esp
- /* Push the initial TSC value from boot block. The low 32 bits are
- * in mm1, and the high 32 bits are in mm2. */
- movd %mm2, %eax
- pushl %eax
- movd %mm1, %eax
- pushl %eax
- /* Restore the BIST result. */
+ /* Need to align stack to 16 bytes at call instruction. Account for
+ the pushes below. */
+ andl $0xfffffff0, %esp
+ subl $4, %esp
+
+ /* push TSC and BIST to stack */
movd %mm0, %eax
- pushl %eax
+ pushl %eax /* BIST */
+ movd %mm2, %eax
+ pushl %eax /* tsc[63:32] */
+ movd %mm1, %eax
+ pushl %eax /* tsc[31:0] */
-before_romstage:
+before_c_entry:
post_code(0x2a)
- /* Call romstage.c main function. */
- call romstage_main
+ call bootblock_c_entry_bist
/* Should never see this postcode */
post_code(POST_DEAD_CODE)
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index a52d3b1..4b49906 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -17,6 +17,7 @@
#include <arch/cpu.h>
#include <arch/io.h>
#include <arch/early_variables.h>
+#include <bootblock_common.h>
#include <console/console.h>
#include <cbmem.h>
#include <cpu/x86/mtrr.h>
@@ -95,8 +96,7 @@
}
/* Entry from cache-as-ram.inc. */
-void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low,
- uint32_t tsc_hi)
+static void romstage_main(uint64_t tsc, uint32_t bist)
{
struct romstage_params rp = {
.bist = bist,
@@ -104,7 +104,7 @@
};
/* Save initial timestamp from bootblock. */
- timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low);
+ timestamp_init(tsc);
/* Save romstage begin */
timestamp_add_now(TS_START_ROMSTAGE);
@@ -131,7 +131,14 @@
platform_enter_postcar();
/* We don't return here */
- return NULL;
+}
+
+/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
+ * keeping changes in cache_as_ram.S easy to manage.
+ */
+asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
+{
+ romstage_main(base_timestamp, bist);
}
static struct chipset_power_state power_state CAR_GLOBAL;
diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h
index 17d711f..31184f9 100644
--- a/src/soc/intel/broadwell/include/soc/romstage.h
+++ b/src/soc/intel/broadwell/include/soc/romstage.h
@@ -29,8 +29,7 @@
void mainboard_romstage_entry(struct romstage_params *params);
void romstage_common(struct romstage_params *params);
-asmlinkage void *romstage_main(unsigned long bist, uint32_t tsc_lo,
- uint32_t tsc_high);
+
void raminit(struct pei_data *pei_data);
struct chipset_power_state;
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index afc8216..b89d948 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -18,6 +18,7 @@
#include <arch/io.h>
#include <arch/cbfs.h>
#include <arch/early_variables.h>
+#include <bootblock_common.h>
#include <bootmode.h>
#include <cbmem.h>
#include <console/console.h>
@@ -64,8 +65,7 @@
}
/* Entry from cache-as-ram.inc. */
-asmlinkage void *romstage_main(unsigned long bist,
- uint32_t tsc_low, uint32_t tsc_hi)
+static void romstage_main(uint64_t tsc, uint32_t bist)
{
struct romstage_params rp = {
.bist = bist,
@@ -75,7 +75,7 @@
post_code(0x30);
/* Save initial timestamp from bootblock. */
- timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low);
+ timestamp_init(tsc);
/* Save romstage begin */
timestamp_add_now(TS_START_ROMSTAGE);
@@ -106,8 +106,14 @@
mainboard_romstage_entry(&rp);
platform_enter_postcar();
+}
- return NULL;
+/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
+ * keeping changes in cache_as_ram.S easy to manage.
+ */
+asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
+{
+ romstage_main(base_timestamp, bist);
}
/* Entry from the mainboard. */