soc/intel/baytrail: Use cbmem_recovery()
For consistency with other soc/intel add s3resume variable,
this helps towards unified chipset_power_state.
Change-Id: Ida04d2292aabb5a366f3400d8596ede0dee64839
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index f922750..f62c998 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -129,6 +129,8 @@
mp->prev_sleep_state = prev_sleep_state;
mp->rmt_enabled = CONFIG(MRC_RMT);
+ int s3resume = prev_sleep_state == ACPI_S3;
+
/* Default to 2GiB IO hole. */
if (!mp->io_hole_mb)
mp->io_hole_mb = 2048;
@@ -141,7 +143,7 @@
&mrc_size);
if (mp->saved_data) {
mp->saved_data_size = mrc_size;
- } else if (prev_sleep_state == ACPI_S3) {
+ } else if (s3resume) {
/* If waking from S3 and no cache then. */
printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
post_code(POST_RESUME_FAILURE);
@@ -180,11 +182,10 @@
ret = mrc_entry(mp);
- if (prev_sleep_state != ACPI_S3) {
- cbmem_initialize_empty();
- } else if (cbmem_initialize()) {
- printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
+ int cbmem_was_initted = !cbmem_recovery(s3resume);
+ if (s3resume && !cbmem_was_initted) {
/* Failed S3 resume, reset to come up cleanly */
+ printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n");
system_reset();
}