soc/amd/cezanne: Allow to specify SPL table path in Kconfig

BUG=b:216096562

Change-Id: I4a5ee335ea8808b595dc65ebafd15baedfbdd06e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 40ba4c1..c0c500d 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -377,6 +377,20 @@
 	depends on HAVE_PSP_WHITELIST_FILE
 	default "3rdparty/amd_blobs/cezanne/PSP/wtl-czn.sbin"
 
+config HAVE_SPL_FILE
+	bool "Have a mainboard specific SPL table file"
+	default n
+	help
+	  Have a mainboard specific SPL table file, which is created by AMD
+	  and put to 3rdparty/blobs.
+
+	  If unsure, answer 'n'
+
+config SPL_TABLE_FILE
+	string "SPL table file"
+	depends on HAVE_SPL_FILE
+	default "3rdparty/amd_blobs/cezanne/PSP/TypeId0x55_SplTableBl_CZN.sbin"
+
 config PSP_SOFTFUSE_BITS
 	string "PSP Soft Fuse bits to enable"
 	default "28 6"
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index 332268c..302deaa 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -127,6 +127,11 @@
 PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE)
 endif
 
+# type = 0x55
+ifeq ($(CONFIG_HAVE_SPL_FILE),y)
+SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE)
+endif
+
 #
 # BIOS Directory Table items - proper ordering is managed by amdfwtool
 #
@@ -196,6 +201,7 @@
 OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse)
 
 OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist)
+OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table)
 
 # Add all the files listed in the config file
 POUND_SIGN=$(call strip_quotes, "\#")
@@ -213,6 +219,7 @@
 		--combo-capable \
 		$(OPT_TOKEN_UNLOCK) \
 		$(OPT_WHITELIST_FILE) \
+		$(OPT_SPL_TABLE_FILE) \
 		$(OPT_PSP_SHAREDMEM_BASE) \
 		$(OPT_PSP_SHAREDMEM_SIZE) \
 		$(OPT_EFS_SPI_READ_MODE) \
diff --git a/src/soc/amd/cezanne/fw.cfg b/src/soc/amd/cezanne/fw.cfg
index f26e215..9757d72 100644
--- a/src/soc/amd/cezanne/fw.cfg
+++ b/src/soc/amd/cezanne/fw.cfg
@@ -28,7 +28,6 @@
 DRTMTA_FILE             TypeId0x47_DrtmTA_CZN.sbin
 KEYDBBL_FILE            TypeId0x50_KeyDbBl_CZN.sbin
 KEYDB_TOS_FILE          TypeId0x51_KeyDbTos_CZN.sbin
-SPL_TABLE_FILE          TypeId0x55_SplTableBl_CZN.sbin
 DMCUERAMDCN21_FILE      TypeId0x58_DmcuEramDcn21.sbin
 DMCUINTVECTORSDCN21_FILE  TypeId0x59_DmcuIntvectorsDcn21.sbin
 PSPBTLDR_AB_FILE        TypeId0x73_PspBootLoader_AB_CZN.sbin