nb/intel/haswell: Use unshifted SPD addresses in mainboards
It's common to use the raw, unshifted I2C address in coreboot. Adapt
mainboards accordingly and perform the shift in MRC glue code.
Tested on Asrock B85M Pro4, still boots and still resumes from S3.
Change-Id: I4e4978772744ea27f4c5a88def60a8ded66520e1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51458
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index b69fb93..9904d5a 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -42,8 +42,8 @@
void mb_get_spd_map(struct spd_info *spdi)
{
- spdi->addresses[0] = 0xa0;
- spdi->addresses[2] = 0xa4;
+ spdi->addresses[0] = 0x50;
+ spdi->addresses[2] = 0x52;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {