drivers/intel/fsp2_0: Send post codes around calls to the blobs
By design, FSP will send POST codes to port 80. In this case we have
both coreboot and FSP pushing post codes, which may make debugging
harder. In order to get a clear picture of where FSP execution begins
and ends, send post codes before and after any call to the FSP blobs.
Note that sending a post code both before and after is mostly useful
on chromeec enabled boards, where the EC console will provide a
historic list of post codes.
Change-Id: Icfd22b4f6d9e91b01138f97efd711d9204028eb1
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14951
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 18aded5..f1deed7 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -42,10 +42,12 @@
platform_fsp_silicon_init_params_cb(&upd);
timestamp_add_now(TS_FSP_SILICON_INIT_START);
+ post_code(POST_FSP_SILICON_INIT);
silicon_init = (void *) (hdr->image_base +
hdr->silicon_init_entry_offset);
status = silicon_init(&upd);
timestamp_add_now(TS_FSP_SILICON_INIT_END);
+ post_code(POST_FSP_SILICON_INIT);
printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
return status;