| commit | c484da1a98610d783131a3a3998c0a999b97f9f5 | [log] [tgz] |
|---|---|---|
| author | Arthur Heymans <arthur@aheymans.xyz> | Sat Nov 09 14:29:04 2019 +0100 |
| committer | Patrick Georgi <pgeorgi@google.com> | Tue Nov 12 18:23:07 2019 +0000 |
| tree | c4e25f9b4fbde15a9962b9d0c7d7117997e26ad1 | |
| parent | fecf77770b8e68b9ef82021ca53c31db93736d93 [diff] [blame] |
sb/intel/i82801jx: Add common code for LPC decode Change-Id: Id706da33f06ceeec39ea50301130770226f0474e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb index 6e0a40a..fb818ff 100644 --- a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb
@@ -45,6 +45,9 @@ # Enable PCIe ports 0,2,3 as slots. register "pcie_slot_implemented" = "0x31" + register "gen1_dec" = "0x00000295" + register "gen2_dec" = "0x001c4701" + device pci 19.0 off end # GBE device pci 1a.0 on end # USB device pci 1a.1 on end # USB