mb/intel/mtlrvp: Update Flash Layout to fit WP_RO within 4MB
This patch updates the MTLRVP flash layout to optimize WP_RO to 4MB.
Changes for chromeos.fmd:
SI_BIOS:
RW_SECTION_A/B: Reduce to 7MB.
RW_LEGACY: Reduce to 1MB.
RW_MISC: Increased to 1MB.
RW_UNUSED: 3MB (reserved)
WP_RO: Reduce to 4MB
Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the
SPI Flash.
BUG=b:277143384
TEST=Able to build and boot intel/mtlrvp with FSP release and debug image.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibd1ea7a3a2cd21928b8e33473c7bdddfad17c636
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
diff --git a/src/mainboard/intel/mtlrvp/chromeos.fmd b/src/mainboard/intel/mtlrvp/chromeos.fmd
index 22dbff5..a5bc538 100644
--- a/src/mainboard/intel/mtlrvp/chromeos.fmd
+++ b/src/mainboard/intel/mtlrvp/chromeos.fmd
@@ -4,34 +4,45 @@
SI_ME
}
SI_BIOS 23M {
- RW_SECTION_A 7092K {
+ RW_SECTION_A 7M {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 64
ME_RW_A(CBFS) 4400K
}
- RW_MISC 152K {
- UNIFIED_MRC_CACHE 128K {
- RECOVERY_MRC_CACHE 64K
- RW_MRC_CACHE 64K
- }
- RW_ELOG(PRESERVE) 4K
- RW_SHARED 4K {
- SHARED_DATA 4K
- }
- RW_VPD(PRESERVE) 8K
- RW_NVRAM(PRESERVE) 8K
- }
- RW_SECTION_B 7092K {
+ # This section starts at the 16M boundary in SPI flash.
+ # MTL does not support a region crossing this boundary,
+ # because the SPI flash is memory-mapped into two non-
+ # contiguous windows.
+ RW_SECTION_B 7M {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 64
ME_RW_B(CBFS) 4400K
}
+ RW_MISC 1M {
+ UNIFIED_MRC_CACHE(PRESERVE) 128K {
+ RECOVERY_MRC_CACHE 64K
+ RW_MRC_CACHE 64K
+ }
+ RW_ELOG(PRESERVE) 16K
+ RW_SHARED 16K {
+ SHARED_DATA 8K
+ VBLOCK_DEV 8K
+ }
+ # The RW_SPD_CACHE region is only used for rex variants that use DDRx memory.
+ # It is placed in the common `chromeos.fmd` file because it is only 4K and there
+ # is free space in the RW_MISC region that cannot be easily reclaimed because
+ # the RW_SECTION_B must start on the 16M boundary.
+ RW_SPD_CACHE(PRESERVE) 4K
+ RW_VPD(PRESERVE) 8K
+ RW_NVRAM(PRESERVE) 24K
+ }
RW_LEGACY(CBFS) 1M
+ RW_UNUSED 3M
# Make WP_RO region align with SPI vendor
# memory protected range specification.
- WP_RO 8M {
+ WP_RO 4M {
RO_VPD(PRESERVE) 16K
RO_SECTION {
FMAP 2K