soc/intel/alderlake: Allow channel 0 for DDR5 memory-down
This matches the change done for DDR4 in commit 8509c25eece8
("soc/intel/alderlake: Allow channel 0 for memory-down").
Fixes detection of the on-board RAM (Samsung M425R1GB4BB0-CQKOD) on the
System76 Lemur Pro 12 (Clevo L140AU). The Clevo L140*U are the only
boards in the tree using mixed memory topology.
Change-Id: I395f898472a9a8f857fd6b0564b95c787b96080b
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c
index 2e64e77..42b6698 100644
--- a/src/soc/intel/alderlake/meminit.c
+++ b/src/soc/intel/alderlake/meminit.c
@@ -70,8 +70,8 @@
* configuration.
*/
.half_channel = BIT(0),
- /* In mixed topologies, channel 1 is always memory-down. */
- .mixed_topo = BIT(1),
+ /* In mixed topologies, either channel 0 or 1 can be memory-down. */
+ .mixed_topo = BIT(0) | BIT(1),
},
},
[MEM_TYPE_LP4X] = {