commit c46bb694955ba80f054bd5770afafbbb929472f6
author Matt Papageorge <matthewpapa07@gmail.com> Thu May 13 15:59:57 2021 -0500
committer Patrick Georgi <pgeorgi@google.com> Fri May 21 06:35:17 2021 +0000
tree b627535399a7341925be6a3e4e60516df9a15f1f
parent 76619b01c84ba2db62310da311de4cf8271154f9

mb/google/guybrush: Enable some PCIe power saving features

Enable ASPM, Common Clock and Clock Power Managment. Accomplish this
by adding the options in the platform Kconfig as well as dxio
descriptors.

BUG=b:187743927
TEST=Boot to ChromeOS and see ASPM, CC and Clock PM enabled with lspci

Change-Id: Iefc4b5b489cb8caf59f21dd4333d7af66ba47c32
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54282
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/guybrush/Kconfig

diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig
index 5326616..0e7d15e 100644
--- a/src/mainboard/google/guybrush/Kconfig
+++ b/src/mainboard/google/guybrush/Kconfig
@@ -32,6 +32,9 @@
 	select MAINBOARD_HAS_CHROMEOS
 	select MAINBOARD_HAS_I2C_TPM_CR50
 	select MAINBOARD_HAS_TPM2
+	select PCIEXP_ASPM
+	select PCIEXP_CLK_PM
+	select PCIEXP_COMMON_CLOCK
 	select PSP_DISABLE_POSTCODES
 	select SOC_AMD_CEZANNE
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI

src/mainboard/google/guybrush/port_descriptors.c

diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c
index cc1fa1a..540d3d1 100644
--- a/src/mainboard/google/guybrush/port_descriptors.c
+++ b/src/mainboard/google/guybrush/port_descriptors.c
@@ -13,6 +13,7 @@
 		.end_logical_lane = 0,
 		.device_number = 2,
 		.function_number = 1,
+		.link_aspm = ASPM_L1,
 		.turn_off_unused_lanes = true,
 		.clk_req = CLK_REQ0,
 		.gpio_group_id = GPIO_29,
@@ -25,6 +26,7 @@
 		.end_logical_lane = 1,
 		.device_number = 2,
 		.function_number = 2,
+		.link_aspm = ASPM_L1,
 		.turn_off_unused_lanes = true,
 		.clk_req = CLK_REQ1,
 		.gpio_group_id = GPIO_70,
@@ -37,6 +39,7 @@
 		.end_logical_lane = 2,
 		.device_number = 2,
 		.function_number = 3,
+		.link_aspm = ASPM_L1,
 		.turn_off_unused_lanes = true,
 		.clk_req = CLK_REQ2,
 		.gpio_group_id = GPIO_18,
@@ -49,6 +52,7 @@
 		.end_logical_lane = 7,
 		.device_number = 2,
 		.function_number = 4,
+		.link_aspm = ASPM_L1,
 		.turn_off_unused_lanes = true,
 		.clk_req = CLK_REQ3,
 		.gpio_group_id = GPIO_40,