cpu/amd/mtrr: Remove topmem global variables
The comments are not correct anymore. With AGESA there is no need to
synchronize TOM_MEMx msr's between AP's. It's also not the best place
to do so anyway.
Change-Id: Iecbe1553035680b7c3780338070b852606d74d15
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index 4aed96b..4b4ab67 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -818,13 +818,6 @@
static void root_complex_enable_dev(struct device *dev)
{
- static int done = 0;
-
- if (!done) {
- setup_bsp_ramtop();
- done = 1;
- }
-
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index fe56736..bd0a5c8 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -737,7 +737,7 @@
sizek = 0;
}
else {
- uint64_t topmem2 = bsp_topmem2();
+ uint64_t topmem2 = amd_topmem2();
basek = 4*1024*1024;
sizek = topmem2/1024 - basek;
}
@@ -900,13 +900,6 @@
static void root_complex_enable_dev(struct device *dev)
{
- static int done = 0;
-
- if (!done) {
- setup_bsp_ramtop();
- done = 1;
- }
-
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index 21b4d69..3d5313a 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -750,7 +750,7 @@
sizek = 0;
}
else {
- uint64_t topmem2 = bsp_topmem2();
+ uint64_t topmem2 = amd_topmem2();
basek = 4*1024*1024;
sizek = topmem2/1024 - basek;
}
@@ -922,13 +922,6 @@
static void root_complex_enable_dev(struct device *dev)
{
- static int done = 0;
-
- if (!done) {
- setup_bsp_ramtop();
- done = 1;
- }
-
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index f1c5e23..332bf1ac 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -770,7 +770,7 @@
pci_domain_read_resources(dev);
/* TOP_MEM MSR is our boundary between DRAM and MMIO under 4G */
- mmio_basek = bsp_topmem() >> 10;
+ mmio_basek = amd_topmem() >> 10;
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
/* if the hw mem hole is already set in raminit stage, here we will compare
@@ -826,7 +826,7 @@
sizek = 0;
}
else {
- uint64_t topmem2 = bsp_topmem2();
+ uint64_t topmem2 = amd_topmem2();
basek = 4*1024*1024;
sizek = topmem2/1024 - basek;
}
@@ -995,13 +995,6 @@
static void root_complex_enable_dev(struct device *dev)
{
- static int done = 0;
-
- if (!done) {
- setup_bsp_ramtop();
- done = 1;
- }
-
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;