intel boards: Use acpi_is_wakeup_s3()
Change-Id: Icab0aeb2d5bf19b4029ca29b8a1e7564ef59a538
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6071
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c
index d4e2986..5d1a4d8 100644
--- a/src/soc/intel/baytrail/ehci.c
+++ b/src/soc/intel/baytrail/ehci.c
@@ -143,7 +143,7 @@
};
/* Don't reset controller in S3 resume path */
- if (acpi_slp_type != 3)
+ if (!acpi_is_wakeup_s3())
reg_script_run_on_dev(dev, ehci_hc_reset);
/* Disable controller if ports are routed to XHCI */
diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c
index 8c6be9f..c31bb00 100644
--- a/src/soc/intel/baytrail/elog.c
+++ b/src/soc/intel/baytrail/elog.c
@@ -73,7 +73,7 @@
if (ps->pm1_sts & WAK_STS) {
elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
- acpi_slp_type == 3 ? 3 : 5);
+ acpi_is_wakeup_s3() ? 3 : 5);
}
if (ps->pm1_sts & PWRBTN_STS) {
diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c
index 019e0a5..12e3ed4 100644
--- a/src/soc/intel/baytrail/refcode.c
+++ b/src/soc/intel/baytrail/refcode.c
@@ -29,15 +29,6 @@
#include <baytrail/ramstage.h>
#include <baytrail/efi_wrapper.h>
-static inline int is_s3_resume(void)
-{
-#if CONFIG_HAVE_ACPI_RESUME
- return acpi_slp_type == 3;
-#else
- return 0;
-#endif
-}
-
static inline struct ramstage_cache *next_cache(struct ramstage_cache *c)
{
return (struct ramstage_cache *)&c->program[c->size];
@@ -140,7 +131,7 @@
};
int ret;
- if (is_s3_resume()) {
+ if (acpi_is_wakeup_s3()) {
return load_refcode_from_cache();
}