tree c30a217d932de31fc242002ec590da0544af38ce
parent 24d40fd698f06b5a19b33547aafd3185a4203096
author Felix Held <felix-coreboot@felixheld.de> 1648070156 +0100
committer Felix Held <felix-coreboot@felixheld.de> 1648234183 +0000

soc/amd/sabrina: update soft fuse bit 15 definition

For SoC that don't support LPC any more the definition of the PSP soft
fuse chain bit 15 has changed. Earlier SoCs that still supported a
physical LPC bus used this bit to determine if the I/O port 0x80 POST
code are sent to LPC or eSPI. Newer SoCs like Sabrina don't have a
physical LPC bus any more and on those this bit selects if the PSP debug
output is sent to the SoC's MMIO UART or an UART on I/O port 0x3F8 that
the needs to be decoded to eSPI.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0bffb6efacc585a1d02a0455b32f7cf8662b3232
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>