commit | c32d7b42bc61fece5c48d0b1db6bb7cb6c28d45f | [log] [tgz] |
---|---|---|
author | Kevin Chiu <kevin.chiu.17802@gmail.com> | Mon Oct 31 15:02:26 2022 +0800 |
committer | Felix Held <felix-coreboot@felixheld.de> | Wed Nov 02 21:35:42 2022 +0000 |
tree | fafb24815d6d0908694cab94a42abb53d6965b8f | |
parent | 8dafcc60793480ad89079b37b26f98ed52dc5ce9 [diff] |
mb/google/brya/var/lisbon: Enable SaGv Enable SaGv support for lisbon BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot pass RMT verification Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Ic7d3203bfe06973b023a38d1aa3d69cce5c3a60c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69013 Reviewed-by: Ricky Chang <rickytlchang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
diff --git a/src/mainboard/google/brya/variants/lisbon/overridetree.cb b/src/mainboard/google/brya/variants/lisbon/overridetree.cb index 67b0d9b..f952c3e 100644 --- a/src/mainboard/google/brya/variants/lisbon/overridetree.cb +++ b/src/mainboard/google/brya/variants/lisbon/overridetree.cb
@@ -6,6 +6,8 @@ end chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value |